Vertical NAND Erase Bias Sequencing for Uniform Channel Potential
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in maintaining uniform erase characteristics across memory cells due to variations in channel potential during erase operations, leading to dispersion issues.
Innovation Solution
The solution involves applying a first bias voltage during an erase operation setup period, followed by a second higher bias voltage after a delay, and an erase inhibit voltage to manage channel potentials, thereby reducing variations and improving erase dispersion characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single bias voltage is applied to all word lines during the erase operation, then the device structure and control logic are simple, but the channel potential varies significantly across different cell strings, causing poor erase dispersion characteristics
Solution Approach 1:
The patent divides the word lines into multiple groups (first word line group and second word line group) and applies different bias voltages to each group during the erase operation. This segmentation allows independent control of channel potential for different cell string sets, improving erase dispersion characteristics by compensating for potential variations across the array.
Solution Approach 2:
The patent applies different bias voltage levels (first bias voltage and second bias voltage) to different word line groups based on their specific positional characteristics and potential conditions. This local quality approach ensures that each region receives the appropriate voltage level to achieve uniform erase characteristics across the entire array.
2Manufacturing precision
If a higher bias voltage is applied to all word lines throughout the entire erase operation, then the channel potential is uniformly increased, but the energy consumption increases and the erase control becomes less precise
Solution Approach 1:
The patent implements a two-period erase operation: a first period where a first bias voltage is applied to all word lines, and a second period where a second (higher) bias voltage is applied only to the second word line group. This periodic action with varying voltage levels achieves channel potential uniformity while controlling energy consumption by applying higher voltage only when and where needed.
Solution Approach 2:
The patent dynamically changes the bias voltage parameter applied to word lines based on the erase operation phase and the specific word line group. By transitioning from a first bias voltage level to a second bias voltage level for specific groups, the system achieves precise control over channel potential uniformity while optimizing energy consumption.
Data Source
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AI summary
A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.