NAND Memory Block Erase Biasing for Uniform Threshold Margins
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As NAND memory devices are scaled down, the spacing between neighboring memory cells becomes smaller, leading to challenges in programming and erasing operations, particularly in three-dimensional configurations where control gates and inter-poly dielectric capacitance is reduced, affecting the efficiency and uniformity of erase operations.
Innovation Solution
A method and apparatus for erasing memory cells in a memory device by dividing the memory block into sub-blocks, applying different bias voltages and voltage step sizes to sub-blocks, and performing separate erase-verify operations to ensure differential erasing speeds and improved uniformity of threshold voltage margins across the memory block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are scaled down to increase density, then storage capacity is improved, but erase operation uniformity deteriorates due to reduced control gate and inter-poly dielectric capacitance
Solution Approach 1:
The memory block is divided into multiple sub-blocks that can be erased independently with different bias voltages. This segmentation allows differential erase operations on different portions of the memory array, compensating for the non-uniform erase characteristics that arise from scaling effects on control gate and inter-poly dielectric capacitance.
Solution Approach 2:
Different bias voltages are applied to different sub-blocks based on their specific erase requirements. Sub-blocks with higher capacitance receive lower bias voltages while sub-blocks with lower capacitance receive higher bias voltages, creating locally optimized erase conditions that compensate for the reduced overall capacitance in scaled devices.
2Productivity
If higher erase voltages are applied to improve erase speed, then productivity is improved, but data retention degradation increases due to excessive stress on memory cells
Solution Approach 1:
The erase operation applies different bias voltages to different sub-blocks based on their specific erase characteristics. Sub-blocks that require faster erasure receive higher bias voltages, while sub-blocks that are more sensitive to voltage stress receive lower bias voltages, optimizing the balance between erase speed and data retention preservation.
Solution Approach 2:
The erase operation is performed dynamically by adjusting bias voltages across multiple erase loops. The control circuitry modifies the bias voltage applied to each sub-block based on verification results from previous erase loops, allowing the system to adapt the erase aggressiveness to the actual state of the memory cells and minimize unnecessary stress.
3Manufacturing precision
If differential bias voltages are applied to sub-blocks to improve erase uniformity, then device complexity increases due to additional control circuitry
Solution Approach 1:
The memory block is segmented into sub-blocks that share common word lines and control structures, allowing differential bias voltage application through minimal additional control circuitry. The segmentation leverages existing memory block architecture while adding only the necessary voltage control capability.
Solution Approach 2:
The control circuitry is designed to perform multiple functions: it manages both the standard unified erase operation and the differential sub-block erase operation. The same control logic can switch between operating modes, and the bias voltage control mechanism serves both erase and verify functions, reducing the need for completely separate control paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the efficiency and uniformity of erase operations, reducing data retention degradation and improving the threshold voltage margin across the memory block, thereby extending the endurance and performance of the memory device.
Implementation Method 1
applying a first bias voltage to a plurality of word lines of the first sub-block and applying a second bias voltage to a plurality of word lines of the second sub-block
Data Source
AI summary
The adaptive erase scheme includes erasing the memory cells of a selected memory block in at least one erase loop. During the at least one erase loop, simultaneously, an erase voltage is applied to a plurality of channels in the selected memory block, a first bias voltage is applied to the plurality of word lines of the first sub-block, and a second bias voltage is applied to the plurality of word lines of the second sub-block. The first bias voltage is different than the second bias voltage so that the memory cells of the first and second sub-blocks are erased at different speeds.