Temperature-Based NAND Erase Block Routing to Reduce Disturb Effects

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Solution Overview

Problem

Existing memory systems face issues with disturb effects such as increased bit error rates and data loss due to the inability to independently erase some memory cells within a block while maintaining data in others, leading to threshold voltage shifts and reduced system performance.

Innovation Solution

Implementing a memory management system that classifies data based on temperature characteristics and routes it to appropriate write cursors, allowing erase blocks within a physical block to have similar temperature characteristics, thereby reducing disturb effects by storing data with similar 'temperatures' within the same physical blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional memory block erase operations are used, then all memory cells in a block are erased together, but this causes disturb effects and threshold voltage shifts when some cells need to retain data

Engineering Contradiction:
Improvedata integrityVSAvoiddisturb effects
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent divides a physical memory block into multiple independent erase blocks, where each erase block can be independently erased. This segmentation allows selective erasure of only those erase blocks that need to be cleared, while preserving data in other erase blocks within the same physical block, thereby eliminating disturb effects on retained data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements different temperature classifications (hot, warm, cold) for different erase blocks within a physical block, allowing each erase block to have optimized characteristics suited to its data access patterns. This local differentiation enables reduced write amplification and improved reliability by matching erase behavior to actual data usage patterns.

Inventive Principle:
Principle #3Local quality

2Reliability

If frequent erase block refreshing is performed to mitigate disturb effects, then data integrity is maintained, but write amplification increases and system performance decreases

Engineering Contradiction:
Improvedata integrityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the physical block into multiple independently erasable blocks, the patent eliminates the need for refreshing entire blocks when only partial data needs updating. This reduces unnecessary write operations and associated write amplification while maintaining data integrity in preserved erase blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameters by introducing temperature-based classification and selective erase block management. Instead of uniform refreshing, the system adjusts erase and write operations based on temperature classifications, reducing unnecessary operations and improving overall system performance.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If multiple write cursors are implemented for temperature-based data routing, then disturb effects are reduced, but device complexity increases

Engineering Contradiction:
Improvedisturb effect reductionVSAvoidmemory management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments write operations into multiple temperature-based streams (hot, warm, cold) with dedicated write cursors for each. This segmentation organizes data flow to prevent mixing of different temperature data, thereby reducing disturb effects while maintaining manageable complexity through structured classification.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different management strategies to different temperature classifications locally. Each temperature class has its own write cursor and erasure characteristics, allowing optimized handling for each data type without requiring complex global management, thus balancing reliability improvement with acceptable device complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12596646B2Memory management among multiple erase blocks coupled to a same string
Publication Date: 2026.04.07 MICRON TECHNOLOGY INC
  • US12596646B2 patent drawing
  • US12596646B2 patent drawing
  • US12596646B2 patent drawing

AI summary

An apparatus can comprise a memory array comprising a plurality of erase blocks and a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller coupled to the memory array can be configured to: receive a write command corresponding to data to be written to the memory array; determine a temperature classification for the data to which the write command corresponds; and, based on the determined temperature classification for the data, route the data to a first write cursor or to one of a number of different write cursors.