NAND String Erase via GIDL Voltage Segmentation

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Solution Overview

Problem

Nonvolatile memory devices with vertically stacked memory cells face challenges in efficiently erasing data due to limitations in voltage distribution and reliability of the erase operation, particularly in maintaining data integrity across multiple erase cycles.

Innovation Solution

The method involves applying distinct voltages to selection lines within the memory block, with a higher voltage applied to the first selection line closest to the erase source and a lower voltage applied to a second selection line farther away, inducing Gate Induced Drain Leakage (GIDL) to efficiently deliver erase voltage to the memory cells, and adjusting the GIDL location based on the number of erase operations to enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single voltage is applied to all selection lines during erase operation, then the device structure is simple, but the voltage distribution is insufficient and erase reliability deteriorates

Engineering Contradiction:

Improveerase operation reliabilityVSAvoidvoltage application complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The selection lines are divided into multiple groups (first selection lines and second selection lines) with different voltage application schemes. First selection lines receive a first voltage while second selection lines receive a second voltage during erase operations, creating segmented voltage distribution that improves erase reliability across different memory block regions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different voltage levels are applied to different selection lines based on their specific locations and functions. The first voltage is applied to selection lines that benefit from higher potential for efficient erase, while the second voltage is applied to other selection lines, optimizing local erase characteristics for each group.

Inventive Principle:

Principle #3Local quality

2Productivity

If higher voltage is applied to first selection line to improve voltage delivery, then erase efficiency improves, but voltage distribution uniformity deteriorates

Engineering Contradiction:

Improveerase operation efficiencyVSAvoidvoltage distribution uniformity

Core Design Contradiction:

ProductivityVSStability of the object's composition

Solution Approach 1:

The selection lines are segmented into first and second groups that receive different voltages. This segmentation allows the system to deliver higher voltage to first selection lines for improved erase efficiency while maintaining appropriate voltage levels on second selection lines, accepting controlled non-uniformity to achieve overall better erase performance.

Inventive Principle:

Principle #1Segmentation

3Reliability

If GIDL is induced by applying different voltages to selection lines, then voltage delivery to memory cells improves, but the risk of harmful leakage current increases

Engineering Contradiction:

Improvedata integrityVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent intentionally induces GIDL (gate-induced drain leakage) current by applying different voltages to first and second selection lines. This converts a traditionally harmful leakage effect into a beneficial mechanism for delivering erase voltage to memory cells that would otherwise be difficult to reach, improving data integrity through controlled exploitation of the GIDL effect.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the efficiency and reliability of data erase operations in nonvolatile memory devices by ensuring consistent voltage delivery and adaptability across multiple erase cycles, maintaining data integrity and capacity.

Implementation Method 1

inducing Gate Induced Drain Leakage (GIDL) to efficiently deliver erase voltage to the memory cells

Methodology Applied

Scientific EffectGate Induced Drain Leakage (GIDL):

Data Source

PatentUS10892019B2Methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the same

Publication Date: 2021.01.12 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.