NAND Flash Cell-Level Erase Strategy for Partial Write Read Reliability
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Solution Overview
Problem
Storage devices face read errors due to voltage leakage between programmed and unprogrammed word lines during partial block writes, especially during power loss events, which are not effectively addressed by existing technologies.
Innovation Solution
Implementing a higher cell level erase operation followed by a lower cell level write operation to create a voltage margin, using techniques like TLC erase before SLC write, reducing overlap and enhancing read reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard erase operation is performed on a block before partial write operations, then the block is ready for programming, but voltage leakage occurs between programmed and unprogrammed word lines causing read errors
Solution Approach 1:
The block is divided into multiple sub-blocks, allowing selective erasure and programming of only the necessary portions. This segmentation prevents voltage leakage from affecting the entire block, as unprogrammed word lines are isolated in separate sub-blocks that are erased independently rather than being adjacent to programmed regions in a fully erased block.
Solution Approach 2:
The block is pre-erased to the highest cell level (e.g., TLC erase) before performing writes at a lower cell level (e.g., SLC write). This preliminary high-level erasure creates a voltage margin by establishing a stronger initial erase state, which prevents voltage leakage from causing read errors during subsequent partial programming operations.
2Reliability
If different cell levels are used for erase and write operations, then voltage margin is increased reducing read errors, but operation complexity increases
Solution Approach 1:
The erase and write operations use different cell level parameters (e.g., TLC erase with 3 bits per cell, SLC write with 1 bit per cell). This parameter change creates a voltage margin between the erase and program states, reducing read errors. The controller manages this complexity by automatically selecting appropriate read voltage thresholds based on the cell level used for writing.
Solution Approach 2:
The controller implements feedback mechanisms to dynamically adjust read voltage thresholds based on the cell level configuration. When data is written at a lower cell level after a higher cell level erase, the controller selects appropriate read thresholds from multiple available sets, ensuring accurate reading while managing the complexity of multi-level operations.
3Reliability
If higher cell level erase is performed before lower cell level write, then voltage margin increases reducing read errors, but erase time increases
Solution Approach 1:
Instead of erasing the entire block to the highest cell level, the patent performs high-level erase only on the specific sub-blocks that will be programmed. This partial action approach maintains the voltage margin benefits where needed while avoiding the time penalty of erasing the entire block, thus reducing overall erase time while maintaining read error reduction.
Data Source
AI summary
In some implementations, a storage device may perform an erase operation, associated with a first cell level, on a block based at least in part on a configuration to perform write operations on the block using a second cell level that is less than the first cell level. The storage device may perform the write operation after performing the erase operation. In some examples, the first cell level associated with the erase operation may be a triple-level cell (TLC) cell level and the second cell level may be a single-level cell (SLC). In other examples, the second cell level may be another cell level so long as the first cell level is higher (e.g., associated with carrying more bits per cell) than the second cell level.