NAND Memory Erase Saturation Mitigation via Selective Programming
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Solution Overview
Problem
In non-volatile memory systems, especially in 3D NAND structures, there is a challenge in erasing memory cells due to physical variations between different regions, leading to erase saturation where faster-to-erase NAND strings can be over-erased, causing damage, while slower-to-erase strings may not complete the erase process efficiently.
Innovation Solution
The proposed solution involves applying a series of erase loops with verify pulses, followed by a program pulse to faster-to-erase NAND strings to increase their threshold voltage, thereby preventing over-erasure and ensuring that slower-to-erase strings complete the erase process without damaging the faster ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase loops are applied to all NAND strings to ensure complete erasure, then slower-to-erase strings can complete the process, but faster-to-erase strings become over-erased and damaged
Solution Approach 1:
The patent applies different voltage conditions to different NAND strings based on their individual erase characteristics. Faster-to-erase strings receive inhibit voltages during verify loops to prevent over-erasure, while slower-to-erase strings continue receiving erase voltages to complete the process. This localized differentiation resolves the contradiction between ensuring complete erasure and preventing damage.
Solution Approach 2:
The patent dynamically adjusts the erase process by monitoring verify results and adapting voltage application in real-time. The controller identifies which strings have completed erasure and modifies subsequent voltage applications accordingly, transitioning from a static uniform erase approach to a dynamic adaptive process that prevents over-erasure while ensuring completeness.
2Object-affected harmful factors
If the erase process is terminated early to prevent over-erasure of faster strings, then damage is avoided, but slower strings do not complete erasure
Solution Approach 1:
The patent segments the erase process into multiple verify loops, with each loop evaluating the erase status of individual NAND strings. This segmentation allows the system to identify which strings have completed erasure and which need continued processing, enabling differentiated treatment that simultaneously prevents over-erasure and ensures completeness.
Solution Approach 2:
The patent implements a feedback mechanism where verify operations provide information about erase completion status to the controller. Based on this feedback, the controller adjusts subsequent erase operations for different strings, applying inhibit voltages to completed strings and continuing erase voltages to incomplete strings, thus resolving the contradiction.
3Ease of manufacture
If uniform erase voltages are applied to all NAND strings, then the process is simple to implement, but physical variations cause inconsistent erase results
Solution Approach 1:
The patent changes the voltage parameters applied to different NAND strings based on their erase characteristics. By modifying voltage magnitude and timing for individual strings, the system compensates for physical variations in the memory structure, achieving uniform erase results despite manufacturing tolerances while maintaining process simplicity through automated control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates erase saturation by allowing slower-to-erase NAND strings to complete the erase process while protecting faster-to-erase strings from damage, ensuring successful and uniform erasure across the memory cells.
Implementation Method 1
The threshold voltage (Vt) of a NAND memory cell can be set to a target Vt by programming charge into a charge storage region such as a charge trapping layer.
Implementation Method 2
a large set of memory cells are erased prior to programming. In some cases, the memory cells of an entire physical block are erased as a group.
Data Source
AI summary
Technology is disclosed herein for a storage system that mitigates erase saturation when erasing memory cells. If erase does not pass after a number of erase loops, the storage system applies a program pulse to memory cells on faster to erase NAND strings. However, memory cells on slower to erase NAND strings are inhibited from programming. The program pulse increases the Vt of memory cells on the faster to erase NAND strings. Then, another erase loop is performed. The process may continue with additional loops, with each loop programming the memory cells on the faster to erase NAND strings followed by an erase pulse to all NAND strings and erase verify. Over-erase of the memory cells on the faster to erase NAND strings is therefore prevented. Moreover, slower to erase NAND strings that may otherwise be a bottleneck do not prevent successful completion of the erase.