NAND Memory Erase Verification for Uniform Threshold Voltage
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Solution Overview
Problem
Existing NAND memory devices face issues with inconsistent erasing speeds and read window margins due to varying wear and tear of the tunneling layer, leading to slower erasing speeds and impaired read performance.
Innovation Solution
A memory device with a peripheral circuit that applies multiple erasure verification voltages sequentially, adjusting the effective erasure voltage based on verification results to ensure consistent erasing extents across blocks, thereby uniforming threshold voltage distributions and enhancing read and erase performances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single effective erasure voltage is applied to all blocks, then the erasing process is simple and fast, but the erasing speeds and threshold voltage distributions become inconsistent across blocks due to varying tunneling layer wear
Solution Approach 1:
The patent applies different erasure verification voltages to different blocks based on their individual wear conditions. The peripheral circuit determines the erasing extent of each block by applying multiple different erasure verification voltages and selects an effective erasure voltage specific to each block's state, thereby achieving consistent erasing speeds across blocks with varying tunneling layer wear without requiring a uniformly complex process for all blocks
Solution Approach 2:
The patent changes the erasure verification voltage parameter to match the wear state of each block. By applying multiple different erasure verification voltages and selecting the appropriate effective erasure voltage based on the determined erasing extent, the system adapts the voltage parameter to achieve consistent erasing performance across blocks with different tunneling layer conditions
2Manufacturing precision
If multiple erasure verification voltages are applied to each block, then consistent erasing extents are achieved across blocks, but the operation time and process complexity increase
Solution Approach 1:
The patent segments the erasure verification process into multiple voltage levels (first, second, and third erasure verification voltages) that are applied sequentially to determine the erasing extent. This segmentation allows the system to efficiently identify the appropriate effective erasure voltage for each block by testing progressively, achieving uniform erasing extent without requiring excessively long operation times
Solution Approach 2:
The patent performs preliminary erasure verification by applying multiple different erasure verification voltages before finalizing the erasure process. This preliminary action of testing with different voltages allows the system to determine the erasing extent in advance and select the appropriate effective erasure voltage, ensuring uniform erasing extent while optimizing the overall operation time
Data Source
AI summary
Implementations of the present disclosure provide a memory device, an operation method thereof, and a memory system. The memory device may include a memory cell array including a plurality of blocks. The memory device may include a peripheral circuit coupled to the memory cell array. The peripheral circuit may be configured to apply a plurality of different erasure verification voltages to a selected block among the plurality of blocks after applying a first effective erasure voltage to the selected block. The peripheral circuit may be configured to determine a second effective erasure voltage applied to the selected block according to a plurality of erasure verification results corresponding to the plurality of different erasure verification voltages. The second effective erasure voltage may be greater than the first effective erasure voltage.