NAND Memory Erase Voltage Feedback Control
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Solution Overview
Problem
Existing memory subsystems face challenges in efficiently performing erase operations on NAND memory devices, as they often require multiple incremental voltage adjustments, leading to excessive wear, increased latency, and degradation of memory cells due to the need for successive erase voltage applications.
Innovation Solution
The memory subsystem controller progressively adjusts the initial erase voltage based on feedback from previous operations, starting with a low value and incrementing it until a successful erase is achieved, thereby reducing the number of voltage applications and minimizing wear on memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple incremental voltage adjustments are applied during erase operations, then the erase operation can be completed, but excessive wear and degradation of memory cells occurs
Solution Approach 1:
The patent applies preliminary action by determining the number of program and erase cycles before the actual erase operation and using this information to set the initial erase voltage. This pre-determination allows the system to start with an appropriate voltage level rather than beginning low and incrementing through multiple adjustments, thereby completing the erase operation while minimizing memory cell wear.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the initial erase voltage based on the number of program and erase cycles. The controller modifies the voltage parameter according to cycle count, selecting from multiple possible initial voltage levels to optimize the erase operation and reduce harmful effects on memory cells.
2Manufacturing precision
If multiple successive erase voltages are applied, then the erase operation achieves desired depth, but latency increases
Solution Approach 1:
The patent uses preliminary action by calculating and setting the appropriate initial erase voltage before the erase operation begins, based on the number of program and erase cycles. This eliminates the need for multiple successive voltage applications and verification loops, thereby achieving the desired erase depth while significantly reducing operation latency.
Solution Approach 2:
The patent applies the skipping principle by directly transitioning to the appropriate initial erase voltage level based on cycle count, rather than incrementally adjusting through multiple voltage levels. This allows the system to rush through the voltage adjustment process and achieve the target erase depth more quickly.
3Manufacturing precision
If higher erase voltage is applied repeatedly, then erase depth is maintained, but memory cell degradation increases
Solution Approach 1:
The patent implements parameter changes by selecting from multiple initial erase voltage levels based on the number of program and erase cycles. Instead of repeatedly applying high voltage, the system adjusts the voltage parameter to match the memory cell's current state, maintaining consistent erase depth while minimizing degradation through optimized voltage selection.
Data Source
AI summary
A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.