NAND Fast CRC Circuit for Two-Bit Programming Error Detection
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Solution Overview
Problem
Existing cyclic redundancy check (CRC) methods in flash memory systems fail to detect two data bit errors within a word, and parity bits often flag only single bit errors, leading to potential data integrity issues.
Innovation Solution
Implementing a fast CRC circuit that performs a polynomial division on programming data to generate CRC data, which is appended to the data before writing, allowing the NAND device to check for errors and report status via an I/O pin, enabling error detection and potential retransmission or correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional CRC methods are used to perform error detection, then error detection capability is provided, but two data bit errors within a word cannot be detected
Solution Approach 1:
The patent segments the 64-bit programming data into eight 8-bit bytes and processes each byte independently through the CRC circuit. This segmentation allows the system to perform multiple CRC calculations on different byte segments, thereby improving the ability to detect errors that traditional single-block CRC methods miss, particularly two-bit errors within a word.
Solution Approach 2:
The patent transitions from traditional single-block CRC processing to multi-dimensional byte-level processing. By organizing data into bytes and processing each byte through separate CRC circuits with different generator polynomials, the system adds a dimensional aspect to error detection that enhances precision without sacrificing reliability.
2Ease of operation
If parity bits are used for integrity check, then single bit errors are flagged, but two data bit errors are not identified
Solution Approach 1:
The patent changes the fundamental parameter of error detection from simple parity bit checking to CRC calculation using generator polynomials. This parameter change transforms the detection capability from identifying only single-bit errors to detecting two-bit errors and other error patterns, while maintaining operational simplicity through automated circuit implementation.
3Reliability
If CRC calculation is performed using shift register or XOR gates, then error detection is achieved, but processing speed is limited
Solution Approach 1:
The patent segments the processing into parallel byte-level operations, with multiple CRC circuits operating simultaneously on different byte segments. This segmentation enables parallel processing that significantly increases productivity while maintaining the reliability of CRC-based error detection through the use of standardized generator polynomials.
Data Source
AI summary
The present disclosure relates generally to a method of detecting errors in programming data. The method includes receiving a frame of encoded data, and performing a pre-calculation operation on the encoded data. The pre-calculation operation includes passing the frame of encoded data through an error detection circuit comprising eight error flag implementation circuits comprising a plurality of two-input XOR logic gates configured to perform a mathematical equation to return a single output value and an eight input OR logic gate coupled to each output of each error flag implementation circuit. The eight input OR logic gate is configured to return an error flag if one or more output values return a value of 1.