NAND Flash Soft Decoding With Adaptive Hypothesis Enumeration

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Solution Overview

Problem

Current NAND flash devices face challenges in improving decoding reliability and reducing decoding complexity, especially in high endurance and retention conditions, with existing soft decoding methods being inefficient and complex.

Innovation Solution

The implementation of an iterative soft decoding method that uses a candidate list and dynamic enumeration size adaptation based on previous iteration results, reducing decoding complexity by nearly half without compromising capability, suitable for NAND flash memories with high code rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional soft decoding methods are used to improve decoding reliability, then decoding complexity increases significantly

Engineering Contradiction:
Improvedecoding reliabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the decoding process into multiple iterations, where each iteration decodes a subset of component codes rather than all codes simultaneously. This segmentation reduces the computational burden per iteration while maintaining overall decoding reliability through cumulative processing across iterations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary decoding of certain component codes in earlier iterations before using their results to inform subsequent decoding operations. By preparing and utilizing preliminary decoding results, the system reduces the complexity of later decoding steps while preserving reliability through the progressive refinement of decoded information.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If exhaustive enumeration over hypotheses is performed to ensure accurate decoding, then decoding latency increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs a limited number of enumerations over hypotheses rather than exhaustive enumeration. By performing partial enumerations that focus on the most likely error patterns, the system achieves sufficient decoding accuracy without the time cost of examining all possible hypotheses.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent employs periodic iterations where enumeration operations are performed at specific intervals rather than continuously for every decoding step. This periodic approach reduces overall latency by concentrating computational effort at strategic points in the decoding process while maintaining accuracy through the structured repetition of enumeration operations.

Inventive Principle:
Principle #19Periodic action

3Device complexity

If dynamic adaptation of enumeration size is implemented to reduce complexity, then decoding capability may be compromised

Engineering Contradiction:
Improvedecoding complexityVSAvoiddecoding capability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent dynamically adjusts the number of enumerations performed based on feedback from previous decoding iterations. By adapting the enumeration size dynamically rather than using a fixed value, the system reduces complexity when possible while preserving decoding capability when needed, achieving an optimal balance between the two competing requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses feedback from extrinsic values and decoding results of previous iterations to determine the appropriate enumeration size for subsequent iterations. This feedback mechanism ensures that the decoding capability is maintained by increasing enumeration when reliability is insufficient, while complexity is reduced by decreasing enumeration when the current decoding performance is adequate.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12095481B2Efficient decoding schemes for error correcting codes for memory devices
Publication Date: 2024.09.17 KIOXIA CORP
  • US12095481B2 patent drawing
  • US12095481B2 patent drawing
  • US12095481B2 patent drawing

AI summary

A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.