NAND Flash SSD Adaptive Scheduling for Read-Write Interference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash SSDs experience significant read tail latency due to read-write and read-erase interference, which violates latency Service Level Objectives (SLOs) as write/program operations have longer latencies and higher frequencies compared to read operations.
Innovation Solution
Implementing a RAID-enabled SSD with novel scheduling and data placement mechanisms that cluster flash chips into groups, where writes are confined to one chip at a time and rotated across chips, and reads are reconstructed using parity stored in a parity-holding flash chip, while disaggregating user writes and garbage collection writes to reduce interference and frequency of garbage collection cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write operations are performed frequently to store data, then data storage capacity and write throughput are improved, but read tail latency increases due to read-write interference
Solution Approach 1:
The flash chip array is segmented into multiple independent groups, where each group contains multiple flash chips. Write operations are confined to specific groups while read operations can access other groups, thereby segmenting the interference paths and allowing simultaneous read and write operations without mutual blocking.
Solution Approach 2:
Parity chips are introduced as intermediary elements in each flash chip group. When a read operation targets a flash chip that is busy with write operations, the controller reconstructs the data using parity information from the parity chip and other available chips in the group, eliminating the need to wait for the write operation to complete.
2Quantity of substance
If garbage collection operations are performed to free up space, then storage space availability is improved, but read tail latency increases due to read-erase interference
Solution Approach 1:
Garbage collection operations are segmented to occur in dedicated flash chip groups that are separate from the groups being accessed for read operations. This spatial segmentation ensures that erase operations during garbage collection do not interfere with read operations in other groups, allowing simultaneous execution without latency penalties.
3Productivity
If multiple flash chips are written to simultaneously to increase write parallelism, then write throughput is improved, but read-write interference increases causing higher read tail latency
Solution Approach 1:
The system segments flash chips into multiple groups and confines write operations within specific groups. This segmentation allows read operations to access different groups simultaneously without interference, maintaining write parallelism within groups while eliminating cross-group read-write conflicts that would increase read tail latency.
Data Source
AI summary
A RAID-enabled solid state drive (SSD) including: a controller connected to a plurality of channels; a plurality of flash chip groups, each including a plurality of flash chips coupled to the plurality of channels, the plurality of flash chips including: a plurality of non-parity flash chips; and i parity flash chips, wherein the controller is configured to write data to the plurality of flash chip groups such that within each of the plurality of flash chip groups only i or less flash chips of the plurality of flash chips are allowed to be written to at the same time, where i is an integer equal to 1 or more.