NAND Flash Multi-Level Storage With High-Resolution ADC Readout
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Solution Overview
Problem
Current flash memory technologies face limitations in storing multiple bits of data per cell, leading to reduced storage density and increased error rates, especially in portable devices where power efficiency and data integrity are crucial.
Innovation Solution
The implementation of multi-level cell (MLC) flash memory systems that use analog-to-digital converters to store and retrieve data values with higher resolution than the original bit representation, allowing for 6, 8, or more bits of information per cell, and dynamically adjust cell resolution based on parameters like temperature, usage, and error levels to enhance data integrity and storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell flash memory is used to store multiple bits per cell, then storage density increases, but data error rates increase
Solution Approach 1:
The patent applies parameter changes by using analog-to-digital converters with higher resolution than the stored data requires. For example, using a 12-bit ADC to store 8-bit data values, creating multiple levels (2^12 = 4096 levels) to represent fewer bits (2^8 = 256 values). This increases the number of distinguishable voltage levels, improving measurement precision and reducing errors while maintaining high storage density.
Solution Approach 2:
The patent replaces traditional binary digital storage with an analog-based multi-level storage system. Instead of using discrete binary states (0 and 1), the system uses continuous analog voltage levels that are converted to digital representations with higher precision than the original data width, thereby reducing quantization errors and improving reliability.
2Measurement precision
If higher resolution analog-to-digital converters are used to increase bits per cell, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent applies partial action by using an analog-to-digital converter with higher resolution than strictly necessary for the data being stored. For example, using a 12-bit converter for 8-bit data storage provides excess precision that improves measurement accuracy and error detection while the additional complexity is managed through efficient converter design and architecture.
3Reliability
If dynamic adjustment of cell resolution is implemented based on operating conditions, then reliability improves, but device complexity increases
Solution Approach 1:
The patent implements dynamic adjustment of cell resolution based on operating conditions such as temperature, read/write cycle counts, and error rates. The system can switch between different resolution modes (e.g., 8-bit, 10-bit, 12-bit) to optimize performance and reliability for different operating scenarios, making the memory system adaptive to changing conditions.
Solution Approach 2:
The system dynamically changes the effective resolution parameter of the memory cells based on operating conditions. By adjusting the number of bits used to represent each cell's voltage level according to temperature, usage patterns, and error rates, the system optimizes the balance between storage capacity, speed, and reliability for different operating scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases storage density, reduces data error rates, and improves power efficiency, enabling higher performance and reliability in portable devices while maintaining low system costs.
Implementation Method 1
Each memory cell is adapted to receive charge during a write operation to an analog voltage corresponding to a data value having a binary representation of more than 4 bits
Implementation Method 2
An analog-to-digital converter converts the analog voltage from each memory cell into a digital representation of the analog voltage during a read operation of each cell
Data Source
AI summary
A system and method, including computer software, for storing digital information uses multiple NAND flash memory cells. Each memory cell is adapted to receive charge during a write operation to an analog voltage that corresponds to a data value having a binary representation of more than 4 bits. An analog-to-digital converter converts the analog voltage from each memory cell into a digital representation of the analog voltage during a read operation of each cell.