NAND Flash Address CRC Checking for High-Speed Transfer Reliability
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Solution Overview
Problem
Conventional NAND flash memories are unable to immediately detect data transmission errors, leading to incorrect accessed addresses or data, which can result in erroneous programming or inaccessibility of stored data, especially with increasing high-speed data transfer rates and noise susceptibility.
Innovation Solution
A data processing method for NAND flash memories that involves a controller and a cyclic redundancy check (CRC) engine to calculate and verify CRC codes for target addresses and data, allowing immediate detection of transmission errors and prompting re-transmissions as necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to achieve high-speed data transfer, then productivity is improved, but transmission errors increase due to noise susceptibility
Solution Approach 1:
The patent applies preliminary action by calculating the CRC check value in advance during data transmission. The controller calculates the CRC check value of the read data before transmission, and the NAND flash memory calculates it again upon receipt, enabling immediate error detection without waiting for the entire transmission to complete, thus maintaining high-speed transfer while ensuring reliability
Solution Approach 2:
The patent implements feedback mechanism where the NAND flash memory compares the calculated CRC check value with the received CRC check value and immediately feeds back the comparison result to the controller. This feedback loop enables real-time error detection and correction, allowing the system to maintain high data transfer rates while ensuring transmission accuracy through continuous verification
2Device complexity
If conventional NAND flash memory operation is used without CRC check, then device complexity is reduced, but transmission errors cannot be detected immediately
Solution Approach 1:
The patent applies self-service principle where both the controller and NAND flash memory independently calculate the CRC check value without requiring external assistance. The controller calculates the CRC value before transmission, and the NAND flash memory calculates it again upon receipt, enabling each component to perform error detection autonomously while maintaining overall system simplicity
Solution Approach 2:
The patent changes the operational parameter by introducing CRC check value calculation and comparison into the existing NAND flash memory operation. This parameter change adds error detection capability to the read/write operations without fundamentally altering the basic memory architecture, thus improving reliability while maintaining relative operational simplicity
Data Source
AI summary
A data processing method for a non-volatile memory device is provided. The non-volatile memory device includes a controller and a NAND flash memory. First, a target command and a corresponding target address are serially transmitted from the controller to the NAND flash memory. Then, the NAND flash memory calculates a first value according to the target address. Moreover, a cyclic redundancy check code corresponding to the target address is transmitted from the controller transmits to the NAND flash memory. Next, the NAND flash memory determines whether a transmission error has occurred by performing a cyclic redundancy check according to the first value and the cyclic redundancy check code. When the transmission error has occurred, a status register is set to inform the controller to re-transmit the target command and the corresponding target address.