NAND Flash Address Mapping for Multi-Plane Access Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND flash memory systems face challenges in realizing the benefits of multi-plane and multi-die architectures due to limitations in logical-to-physical address translation, leading to inefficient data access and increased latency, particularly in systems with random access patterns and device addressing restrictions.
Innovation Solution
A memory controller and host collaboration mechanism that provides direct physical address assignment and management, allowing hosts to plan data storage and access in a manner consistent with multi-plane and multi-die capabilities, reducing the need for memory controller translation and enhancing interleaving and bus utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If logical-to-physical address translation is performed by the memory controller, then data can be stored and retrieved, but latency increases and system performance deteriorates
Solution Approach 1:
The patent extracts the address translation function from the memory controller and relocates it to the host system. The host maintains a translation layer that maps logical addresses to physical addresses, eliminating the need for the memory controller to perform translation operations. This extraction reduces the memory controller's workload and eliminates translation-related latency in the data path.
Solution Approach 2:
The host performs address translation in advance before data access operations. By pre-translating logical addresses to physical addresses and organizing data accordingly in the storage device, the system eliminates the need for real-time translation during data access, thereby reducing latency and improving overall system performance.
2Quantity of substance
If multi-plane and multi-die architectures are used, then storage capacity increases, but addressing restrictions and device limitations reduce access efficiency
Solution Approach 1:
The patent introduces a new dimension of address management by implementing a hierarchical addressing scheme that explicitly accounts for multi-plane and multi-die structures. The translation layer organizes data across multiple planes and dies using a structured mapping approach that respects device addressing restrictions while enabling efficient parallel access patterns.
Solution Approach 2:
The patent segments the address space and data organization to align with the physical multi-plane and multi-die architecture. By dividing the logical address space into segments that map to specific planes and dies, the system can independently manage and access different segments, thereby improving access efficiency while maintaining the benefits of increased storage capacity.
3Adaptability or versatility
If random access patterns are implemented, then data retrieval flexibility improves, but latency and bus idle time increase
Solution Approach 1:
The host performs preliminary organization of data in physical storage locations based on anticipated access patterns. By pre-positioning data that is likely to be accessed together or in sequence, the system reduces the impact of random access patterns, minimizing bus idle time and latency while maintaining retrieval flexibility.
Solution Approach 2:
The translation layer incorporates feedback mechanisms that monitor access patterns and dynamically adjust the mapping of logical to physical addresses. By learning from actual access behavior, the system can optimize data placement to reduce latency and bus idle time while maintaining the flexibility needed for random access patterns.
Data Source
AI summary
This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.