NAND Flash Bus Contention Avoidance via Addressing Synchronization
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Solution Overview
Problem
In NAND flash memory systems, bus contention occurs due to misaligned address bits in different addressing schemes used by memory units, leading to erroneous responses and potential failure of entire storage devices if failing memory units are not isolated.
Innovation Solution
Implementing a scheme to synchronize the addressing schemes of all memory units within a storage device to match the scheme of passing units, ensuring aligned address bits and preventing bus contention by configuring failing units to the same addressing scheme as passing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory units use different addressing schemes (passing units use one scheme, failing units use another), then initialization can proceed for all units, but bus contention occurs due to misaligned address bits
Solution Approach 1:
The patent changes the addressing scheme parameter of failing memory units to match the passing units. Specifically, it modifies the address bit alignment by adjusting the chip select signal timing or address decoding logic for failing units, transforming their addressing parameters to be compatible with the bus protocol used by passing units, thereby eliminating bus contention while maintaining initialization success
2Object-generated harmful factors
If failing memory units are isolated to prevent bus contention, then bus contention is avoided, but storage device capacity decreases
Solution Approach 1:
The patent applies local quality by making each memory unit's addressing characteristics unique to its performance status. Passing units use the standard addressing scheme while failing units use a modified scheme with adjusted address bit alignment. This localized adaptation allows each unit to be optimized for its specific condition, enabling all units to function simultaneously without bus contention while preserving total storage capacity
3Object-generated harmful factors
If all memory units use the same addressing scheme, then bus contention is prevented, but failing units cannot be distinguished and isolated
Solution Approach 1:
The patent implements feedback mechanisms where the controller monitors the response of each memory unit during initialization and operation. By observing whether a unit responds correctly to address signals and data commands, the controller can identify which units are failing despite using the same addressing scheme. This feedback loop enables continuous detection and isolation of problematic units while maintaining uniform addressing for bus contention prevention
Data Source
AI summary
In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.