NAND Flash Memory Cell Air Gap Sidewall Design
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Solution Overview
Problem
The miniaturization of NAND flash memory cells is hindered by limitations in the size of the floating gate, gate conductor, and inter-poly dielectric film, which affect capacitance ratios and data retention, making it difficult to scale down memory cells further.
Innovation Solution
The introduction of an air gap between the floating gate and the gate conductor, along with a thinner inter-poly dielectric film on one sidewall, reduces the cell pitch and maintains capacitance ratios, allowing for smaller cell sizes while ensuring reliable programming and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the floating gate, gate conductor, and inter-poly dielectric film are miniaturized to reduce cell size, then cell pitch is reduced, but capacitance ratios deteriorate and data retention reliability is compromised
Solution Approach 1:
The patent applies local quality by forming an air gap selectively on one sidewall of the floating gate while maintaining the inter-poly dielectric film on the other sidewall. This localized modification allows the cell pitch to be reduced without uniformly compromising the capacitance structure, thereby maintaining data retention reliability while achieving miniaturization.
Solution Approach 2:
The patent introduces asymmetry by creating an uneven configuration where an air gap is present on one sidewall of the floating gate but not on the other. This asymmetric structure optimizes the balance between reducing cell pitch and maintaining sufficient capacitance ratio for reliable data retention, resolving the technical contradiction.
2Length of moving object
If the inter-poly dielectric film is made thinner to reduce cell size, then cell pitch is reduced, but manufacturing precision and reliability are compromised
Solution Approach 1:
The patent extracts the inter-poly dielectric film from one sidewall of the floating gate, replacing it with an air gap. This removal allows the cell pitch to be reduced without requiring ultra-thin film control on both sidewalls, thereby maintaining manufacturing precision while achieving miniaturization.
Solution Approach 2:
The patent applies local quality by selectively removing the inter-poly dielectric film only from one sidewall while maintaining it on the other. This localized approach reduces the overall cell pitch without demanding extreme manufacturing precision across the entire structure, resolving the contradiction between miniaturization and manufacturing precision.
3Length of moving object
If the floating gate size is reduced to miniaturize the cell, then cell pitch is reduced, but capacitance ratio deteriorates affecting programming reliability
Solution Approach 1:
The patent applies local quality by creating an air gap on one sidewall of the floating gate, which allows the floating gate size to be reduced while compensating for the capacitance loss through the asymmetric configuration. This maintains programming reliability despite miniaturization.
Solution Approach 2:
The patent uses asymmetry by forming an air gap on only one sidewall of the floating gate. This asymmetric structure allows for reduced floating gate dimensions while maintaining sufficient capacitance ratio for reliable programming, as the remaining inter-poly dielectric film on the other sidewall provides the necessary electrical coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cell pitch by approximately 25% and maintains capacitance ratios, enabling efficient programming and data retention, thus facilitating the miniaturization of NAND flash memory cells without compromising reliability.
Implementation Method 1
The introduction of an air gap between the floating gate and the gate conductor, along with a thinner inter-poly dielectric film on one sidewall, reduces the cell pitch and maintains capacitance ratios
Data Source
AI summary
According to one embodiment, a nonvolatile memory includes the following structure. A first gate insulating film, a first floating gate, a second gate insulating film and a gate electrode are stacked on a semiconductor region between source and drain electrodes. A second floating gate is formed on a first side surface of the first floating gate. A first insulating film is formed between the first and second floating gates and has an air gap. A third floating gate is formed on a second side surface of the first floating gate on the opposite side of the first side surface. A second insulating film is formed between the first and third floating gates.