NAND Flash Memory Air Gaps Reduce RC Delay
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Solution Overview
Problem
Existing NAND flash memory technologies face performance issues due to device-to-device RC delay caused by close proximity of adjacent memory cells, leading to mutual interference during operations like write, read, or erase.
Innovation Solution
The method involves forming air gaps between adjacent selection gates and control gates by using a hard mask layer to control etching processes, ensuring larger spacings between these structures and depositing a dielectric layer to create these gaps, which reduces parasitic capacitance and RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are placed in close proximity to increase integration density, then integration density is improved, but device-to-device RC delay and mutual interference increase
Solution Approach 1:
An air gap is introduced as an intermediary structure between adjacent control gates and selection gates. This air gap acts as a mediator that reduces parasitic capacitance coupling between neighboring gates, thereby decreasing RC delay and mutual interference while allowing memory cells to remain in close proximity for high integration density
Solution Approach 2:
The air gap structure creates a porous or void space between adjacent gate structures. This porous configuration reduces the dielectric constant in the region between gates, lowering parasitic capacitance and RC delay without requiring increased spacing between memory cells
2Reliability
If air gaps are formed between adjacent gates to reduce RC delay, then device-to-device interference is reduced, but fabrication process complexity increases
Solution Approach 1:
A hard mask layer is formed on the surface of the control gates before the etching process. This preliminary masking action defines the precise location and dimensions of the air gaps, enabling controlled removal of material to create the desired void spaces between adjacent gates
Solution Approach 2:
Traditional mechanical spacing methods are replaced with a deposition and etching process that creates air gaps through material removal. The hard mask layer guides selective etching to form precise air gaps, replacing simpler but less accurate mechanical spacing approaches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the RC delay between adjacent memory cells, minimizing mutual interference and enhancing the performance and integration density of NAND flash memory by maintaining consistent performance across different locations.
Implementation Method 1
removing part of a width of the selection gate and part of a width of the control gates by using the hard mask layer as a mask to perform a back-etching process onto the stacked gate structure
Implementation Method 2
performing a deposition process to form a dielectric layer filling the notch, wherein air gaps are formed in the dielectric layer between the adjacent selection gates and between the adjacent control gates
Data Source
AI summary
A method is provided for fabricating a NAND flash memory. The method includes providing a semiconductor substrate having an isolation material layer formed on the semiconductor substrate, a selection gate material layer formed on the isolation material layer, and a plurality of alternately stacked gate dielectric material layers and control gate material layers formed on the selection gate material layer; forming a hard mask layer having a plurality of openings on a surface of the uppermost control gate material layer; forming a stacked gate structure on the semiconductor substrate, wherein the stacked gate structure includes a selection gate on the semiconductor substrate and control gates on the selection gate, and a width of the stacked gate structure is the same as a width of the hard mask layer on a top surface of the stacked gate structure; isolating the selection gate and the control gates by a gate dielectric layer.