NAND Flash Memory Asymmetric Interval Layout for Leakage Suppression
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Solution Overview
Problem
Current NAND type flash memory technologies face issues with current leakage due to Gate Induced Drain Leakage (GIDL) during programming actions, leading to variations in memory cell thresholds, especially when intervals between transistors and memory cells become nano-scale, affecting programming reliability and chip size.
Innovation Solution
The semiconductor memory device incorporates an asymmetric layout structure where the interval between the source line select transistor and the memory cell is greater than the interval between the bit line select transistor and the memory cell, and employs specific manufacturing methods to form these intervals, including the use of spacer layers and photoresist patterns to etch the memory cell gates, thereby suppressing current leakage and maintaining a reliable programming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the interval between transistors and memory cells is reduced to nano-scale, then chip size is reduced, but current leakage due to Gate Induced Drain Leakage (GIDL) increases
Solution Approach 1:
The patent applies asymmetry by setting different interval lengths between the source line select transistor and memory cell (first interval) versus between the bit line select transistor and memory cell (second interval). Specifically, the first interval is configured to be greater than the second interval, creating an asymmetric layout that suppresses GIDL current leakage while maintaining compact chip size. This asymmetric arrangement optimizes the electrical characteristics by reducing the harmful interaction between the source line select transistor and adjacent memory cells during programming operations.
2Object-generated harmful factors
If the interval between source line select transistor and memory cell is increased, then current leakage is suppressed, but chip area increases
Solution Approach 1:
The patent applies local quality by selectively increasing the interval only where it is most needed - between the source line select transistor and the memory cell (first interval > second interval). This localized adjustment targets the specific area where GIDL current leakage occurs during programming, suppressing harmful effects without unnecessarily expanding the overall chip area. The asymmetric interval configuration optimizes the trade-off between current leakage suppression and area efficiency.
Data Source
AI summary
A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).