NAND Flash Bad Block Management Using Time-Multiplexed Comparator
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Solution Overview
Problem
Conventional semiconductor memory devices require multiple comparator circuits per plane to identify bad blocks, leading to increased chip size as integration increases, which is inefficient and costly.
Innovation Solution
A semiconductor memory device utilizing a single comparator circuit to determine bad blocks across multiple planes by sequentially comparing input addresses with stored bad block addresses, generating bad-block pulses to select appropriate blocks, thereby reducing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple comparator circuits are used per plane to identify bad blocks, then bad block identification accuracy is improved, but chip size increases
Solution Approach 1:
The patent combines multiple comparator circuits into a single shared comparator circuit that sequentially serves multiple planes. Instead of having dedicated comparators for each plane, the same comparator is time-multiplexed across different planes, reducing the total number of comparators from N (where N is the number of planes) to 1, thereby significantly reducing chip area while maintaining bad block identification capability
Solution Approach 2:
The patent implements periodic action by sequentially enabling different planes at different time periods. The controller activates one plane at a time, performs bad block identification using the shared comparator, then moves to the next plane. This time-division multiplexing approach allows a single comparator to serve multiple planes periodically, resolving the contradiction between identification accuracy and chip size
2Reliability
If multiple comparator circuits are used per plane, then bad block detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple independent comparator circuits into a single shared resource. Instead of having separate detection pathways for each plane that would increase circuit complexity, the system consolidates the comparison function into one circuit that is sequentially applied to different planes through controlled enabling signals, thereby reducing device complexity while preserving detection capability
Solution Approach 2:
The shared comparator circuit is designed to be universal, serving multiple planes through time-division multiplexing. The same hardware resource performs the bad block identification function for different planes at different times, eliminating the need for plane-specific comparator circuits and reducing overall device complexity
Data Source
AI summary
A semiconductor memory device capable of reducing the size of a NAND flash memory device includes a latch unit configured to store a bad block address, a comparator configured to compare the bad block address with an access address so as to output a bad-block detection signal, and a bad block controller configured to sequentially output a plurality of bad block pulses corresponding to the bad-block detection signal during a predetermined period in response to a plurality of bad-block flag signals that are sequentially activated.