NAND Flash Bad Block Detection via Multi-Plane Ready/Busy Signal
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Solution Overview
Problem
Current semiconductor memory systems face inefficiencies in detecting bad blocks in NAND flash memory, leading to increased time and potential errors during read, write, and erase operations.
Innovation Solution
A test system and method that utilizes a non-volatile memory device operating in multi-plane mode, generating a ready/busy signal based on the progress of an erase loop to differentiate between normal and bad blocks, allowing for reduced processing time by terminating the erase loop early when all blocks are detected as bad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full erase loop is executed for bad block detection in multi-plane mode, then detection accuracy is improved, but test time increases
Solution Approach 1:
The patent divides the multi-plane memory blocks into individual plane blocks for independent detection. Instead of executing a complete erase loop across all planes simultaneously, the system segments the detection process to test each plane's blocks separately, allowing early termination when bad blocks are identified in specific planes without wasting time on other planes.
Solution Approach 2:
The patent implements partial action by executing the erase loop only for the necessary number of planes rather than all planes. When bad blocks are detected in certain planes, the system performs partial detection on remaining planes or terminates early, avoiding excessive execution of the full erase loop while still maintaining adequate detection accuracy.
2Productivity
If multi-plane mode is used for bad block detection, then productivity is improved, but complexity of detection increases
Solution Approach 1:
The patent introduces dynamic control mechanisms that adjust the detection process based on real-time results. The system dynamically modifies the erase loop execution by detecting bad blocks in each plane and adjusting subsequent plane detections accordingly, enabling early termination when all remaining blocks are confirmed good or when bad blocks are found in all planes, thus managing complexity while maintaining productivity.
Solution Approach 2:
The patent implements feedback control where detection results from each plane are fed back to control the continuation of the erase loop for subsequent planes. This feedback mechanism allows the system to intelligently terminate the detection process early when unnecessary, reducing the effective complexity of operation while maintaining high productivity through optimized multi-plane processing.
Data Source
AI summary
A test system includes a non-volatile memory device that includes a plurality of memory blocks operating in a multi-plane mode, and a test machine that detects a bad block of the non-volatile memory device. The non-volatile memory device generates a ready/busy signal which is based on whether an erase loop for detection of the bad block progresses. When at least one normal block is detected from the plurality of memory blocks included in planes operating in the multi-plane mode, the non-volatile memory device generates the ready/busy signal having a first busy interval. When all the memory blocks included in the planes operating in the multi-plane mode are detected as bad blocks, the non-volatile memory device generates the ready/busy signal having a second busy interval shorter than the first busy interval.