NAND Flash Bad-Block Scanning With Cache Read Preloading
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Solution Overview
Problem
Existing methods for scanning bad blocks in NAND flash memory are time-consuming and lack effective solutions beyond hardware acceleration.
Innovation Solution
A method and circuit system that utilize a cache read command to preload memory page data to a cache during the scanning process, minimizing the impact of read busy time by issuing subsequent cache read commands during memory busy times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional read command is used to read data from flash memory, then the data can be read out, but the read busy time causes significant delay in the scanning process
Solution Approach 1:
The patent introduces a cache read command that preloads data from flash memory into an internal cache before the actual read operation is needed. This preliminary action allows the controller to prepare data in advance, reducing the impact of read busy time during the scanning process and enabling faster subsequent access to the data.
2Productivity
If the controller waits for the memory to finish processing before issuing the next command, then the memory processing is completed, but the processor time is wasted during the wait period
Solution Approach 1:
The patent enables continuous operation by allowing the controller to issue multiple cache read commands in sequence without waiting for each command to complete. The controller can continuously preload data into the cache while the memory processes previous commands, eliminating idle wait time and maintaining continuous productive action throughout the scanning process.
3Loss of time
If hardware acceleration is used to speed up bad block scanning, then the scanning time is reduced, but the device complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the flash memory controller's internal cache automatically preloads data during memory busy periods without requiring external processor intervention. The cache management and data preloading operations are handled autonomously by the controller hardware, achieving acceleration without adding complex external hardware components.
Data Source
AI summary
A method for scanning bad block of a memory and a circuit system thereof are provided. In a procedure of scanning bad blocks of the memory, the circuit system uses a cache read command that is adapted to a process of continuously reading a plurality of memory pages of the memory. The cache read command loads a memory page data to a cache of the memory in advance, and then reads the memory page data from the cache at a next instruction cycle. Next, the cache read command loads a next memory page data to the cache. These steps are repeated until the procedure of scanning bad blocks of the memory is completed. The method can effectively reduce the time for the memory to prepare the next page data so as to reduce the impact of the busy time of the memory on time performance.