NAND Flash BER Classification for Low-Latency SSD Reads
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Solution Overview
Problem
Solid-state drives (SSDs) face challenges in reducing latency and improving quality of service (QoS) due to increasing error rates and inter-cell interference in NAND flash memory, which affects the efficiency of read operations.
Innovation Solution
The method involves a controller in an SSD that estimates and classifies the bit error rate (BER) of memory cells based on threshold voltage distributions. This information is used to execute different read flows, either with or without hard decision decoding stages, depending on the BER threshold, thereby optimizing read operations and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes (ECC) are used to correct read errors in NAND flash memories, then reliability is improved, but read latency increases
Solution Approach 1:
The patent dynamically changes the decoding parameter (hard decision stage execution) based on the estimated BER parameter. When BER is low, hard decision decoding is skipped; when BER is high, it is executed. This adaptive parameter adjustment resolves the contradiction by making the error correction capability conditional rather than fixed, reducing unnecessary latency while maintaining reliability when needed.
2Measurement precision
If multiple reads at varying threshold voltages are performed to improve read accuracy, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent dynamically adjusts the read operation parameters based on estimated BER and classification results. Instead of always performing multiple reads at varying threshold voltages, the system adapts the read strategy: when BER is estimated to be low and classification indicates favorable conditions, fewer reads are performed; when conditions deteriorate, additional reads with adjusted threshold voltages are executed. This resolves the contradiction by making read accuracy conditional rather than universal.
Solution Approach 2:
The patent introduces dynamic adaptation in the read operation flow by using real-time BER estimation and classification to determine the appropriate read strategy. The system transitions from a static multi-read approach to a dynamic approach where the number and parameters of reads are adjusted based on current memory block conditions, thereby optimizing both accuracy and speed.
3Reliability
If hard decision decoding stages are executed to correct errors, then reliability is improved, but read latency increases
Solution Approach 1:
The patent dynamically changes the decoding parameter (execution of hard decision stage) based on the estimated BER parameter. When BER is low, hard decision decoding is skipped to reduce latency; when BER is high, it is executed to ensure reliability. This adaptive parameter adjustment resolves the contradiction by making error correction conditional rather than universal.
Data Source
AI summary
A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.