NAND Flash Bit Error Rate Estimation During Programming

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Solution Overview

Problem

Conventional methods for estimating bit error rates (BER) in NAND flash memory devices are time-consuming and do not provide BER during the programming process, affecting the reliability and endurance of the memory devices.

Innovation Solution

Implementing a method to estimate BER during programming by using multiple verify threshold values for each voltage threshold, determining under- and over-programmed cells, and updating a read status field register with estimated BER values, allowing for adaptive programming parameter adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional methods are used to estimate bit error rates, then measurement precision is achieved, but loss of time occurs due to the time-consuming nature of the process

Engineering Contradiction:

Improvebit error rate estimation accuracyVSAvoidprogramming time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing BER estimation during the programming process itself rather than after completion. Multiple verify threshold values are used to detect under-programmed and over-programmed cells in real-time, allowing BER estimation to be integrated into the programming workflow and eliminate separate measurement time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter of verify threshold values from a single value to multiple values during the programming process. By using multiple verify threshold values, the system can detect programming errors at different stages, enabling real-time BER estimation without extending the overall programming time.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If programming speed is increased, then productivity is improved, but reliability deteriorates due to insufficient programming verification

Engineering Contradiction:

Improveprogramming speedVSAvoidprogramming reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements feedback by using multiple verify threshold values to continuously monitor programming status and detect under-programmed and over-programmed cells during the programming process. This real-time feedback mechanism allows the system to maintain high programming speed while ensuring reliability through immediate error detection and correction.

Inventive Principle:

Principle #23Feedback

3Measurement precision

If multiple verify threshold values are used for BER estimation, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

ImproveBER estimation precisionVSAvoidprogramming process complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the multiple verify threshold mechanism to serve multiple functions simultaneously: it estimates BER, detects under-programmed cells, detects over-programmed cells, and provides real-time programming status feedback. This multi-functionality approach increases measurement precision while minimizing the addition of separate complex components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10658058B1Bit error rate estimation for NAND flash memory

Publication Date: 2020.05.19 KIOXIA CORP

AI summary

The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.