NAND Flash Memory Bit Line Capacitance Coupling Read
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In nonvolatile semiconductor memory devices, particularly NAND type flash memory, the challenge lies in effectively reading threshold distributions in the negative region without increasing process costs or chip area, as existing methods require negative potentials on word lines or large boosters for bit lines, leading to potential disturbances and errors.
Innovation Solution
The solution involves utilizing capacitance coupling between bit lines to apply negative potentials for reading, allowing for discrimination of threshold distributions in the negative region using only positive potentials on word lines, without the need for a booster with large driving ability, thus eliminating variations in bit line biases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If negative potentials are applied to word lines to read threshold distributions in the negative region, then data reading capability is improved, but device configuration must be modified and process cost increases
Solution Approach 1:
The patent introduces bit lines as intermediaries to transfer negative potentials from word lines to cell transistors. Instead of directly applying negative potentials to word lines (which requires well modification), the system uses bit lines as mediators that can be pre-charged to negative potentials and then couple these potentials to the cell transistors through capacitance coupling during the read operation.
Solution Approach 2:
The patent shifts the potential application from the word line dimension to the bit line dimension. By pre-charging bit lines to negative potentials and using capacitance coupling during the read operation, the system achieves negative potential reading without modifying the word line driver well configuration, effectively moving the problem to a different dimensional approach.
2Ease of operation
If boosters are added to apply bias to bit lines for reading negative region distributions, then reading capability is improved, but chip area increases
Solution Approach 1:
The patent enables the bit lines to self-generate the necessary negative potentials through capacitance coupling during the read operation. The bit lines are pre-charged to negative potentials, and during the read cycle, the coupling between bit lines and cell transistors automatically transfers these potentials without requiring external booster circuits, making the system self-sufficient and eliminating the need for additional area-consuming booster components.
Solution Approach 2:
The patent changes the potential parameter of bit lines from standard positive potentials to negative potentials through pre-charging. By storing negative potentials in the bit lines during off-periods and then utilizing these potentials during read operations through capacitance coupling, the system achieves the desired reading capability without requiring additional booster circuits that would increase chip area.
3Quantity of substance
If write potential and read potential are increased to widen threshold distribution range, then data storage capacity is improved, but disturb increases causing write errors and read errors
Solution Approach 1:
The patent segments the potential application process into distinct phases: pre-charging bit lines to negative potentials during off-periods, and then using capacitance coupling during read operations. This segmentation allows the system to achieve the necessary potential ranges for multi-level storage without applying excessively high potentials simultaneously, thereby reducing disturb and error rates while maintaining data storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient reading of threshold distributions in the negative region without modifying the device or increasing chip area, reducing the risk of write and read errors and improving data retention characteristics.
Implementation Method 1
making the first bit line floating, after pre-charging the first bit line to a first potential, varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state
Data Source
AI summary
A memory device includes a control circuit which controls a semiconductor region, a first bit line, a second bit line and a source line. The control circuit is comprised of means for making the first bit line floating, after pre-charging the first bit line to a first potential, means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state, and means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential.