NAND Flash Memory Bit Line Charging Staggering
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Solution Overview
Problem
As NAND type flash memory capacity increases, the number of bit lines grows, leading to high currents during write operations due to the need to charge bit lines up to a higher voltage, which can result in excessive current flow and efficiency issues, especially as device miniaturization advances and bit line capacitance increases.
Innovation Solution
The implementation of a control circuit that varies the timing of charging bit lines across multiple planes during write operations, using bit line clamp voltage line drivers to apply the voltage VTH at different times to each plane, thereby distributing the peak current and reducing the total current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bit lines is increased to increase memory capacity, then memory capacity is improved, but current consumption during write operations increases
Solution Approach 1:
The memory device is divided into multiple independent planes, each with its own bit line clamp voltage line driver. This segmentation allows different planes to operate independently with staggered timing, so that not all bit lines are charged simultaneously, thereby reducing peak current consumption while maintaining high memory capacity
Solution Approach 2:
The bit line clamp voltage line drivers in different planes are activated at different time periods during write operations. This periodic/staggered action distributes the current demand over time, preventing simultaneous charging of all bit lines and thus reducing peak current consumption while still achieving high memory capacity
2Manufacturing precision
If bit line capacitance is increased due to device miniaturization, then integration density is improved, but current flow during charging increases
Solution Approach 1:
The bit line charging operation is segmented across multiple planes with independent control. Each plane's bit line clamp voltage line driver charges bit lines at different times, which distributes the harmful current flow effect over time and prevents excessive simultaneous current flow, while allowing continued device miniaturization and high integration density
Solution Approach 2:
The charging of bit lines is performed in periodic/staggered fashion across different planes rather than simultaneously. This periodic action reduces the peak current flow that would otherwise occur when charging all bit lines at once, while still achieving high integration density through continued miniaturization
Data Source
AI summary
Nonvolatile semiconductor memory device according to one embodiment includes: a plurality of planes; a memory cell array provided in the plurality of planes respectively; bit lines; and a control circuit. Each memory cell array is configured as an array of NAND cell units each including a memory string. The memory string includes a plurality of nonvolatile memory cells connected in series. The bit lines are connected to a first end of the NAND cell units, respectively. The control circuit controls a write operation of charging the bit lines up to a certain voltage value, and then setting data in the nonvolatile memory cells to a certain threshold voltage distribution state. The control circuit is configured to be capable of executing an operation of charging the bit lines in a write operation by varying timings of starting charging the bit lines among the plurality of planes.