NAND Flash Bit Line Charge Discharge Circuit
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Solution Overview
Problem
In NAND type flash memory, increased parasitic capacitance and sheet resistance due to miniaturization of memory cells lead to longer discharge times for bit lines, affecting the speed of read, write, and erase operations.
Innovation Solution
A nonvolatile semiconductor storage device is configured with a charge/discharge circuit formed in a well, which cooperates with the sense amplifier circuit to charge or discharge bit lines, reducing the load capacitance and resistance, thereby shortening the discharge time and enhancing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase storage density, then storage capacity is improved, but parasitic capacitance and sheet resistance of bit lines increase, causing discharge time to increase
Solution Approach 1:
The discharge function is segmented between two separate circuits: the sense amplifier circuit and the charge/discharge circuit. The sense amplifier circuit handles discharge through its pull-down transistors, while the charge/discharge circuit provides additional discharge capability through dedicated discharge transistors. This segmentation allows the bit line to be discharged through multiple parallel paths, reducing the overall discharge time despite increased parasitic capacitance from miniaturization.
2Quantity of substance
If memory cells are miniaturized, then storage density is improved, but the load capacitance and resistance of bit lines increase, reducing operation speed
Solution Approach 1:
The sense amplifier circuit and charge/discharge circuit are merged into a unified system that cooperates to charge and discharge bit lines. The charge/discharge circuit supplements the sense amplifier circuit's discharge capability, creating a combined discharge path that overcomes the increased load capacitance and resistance caused by miniaturization, thereby maintaining high operation speed.
3Loss of time
If a charge/discharge circuit is added to reduce discharge time, then discharge speed is improved, but device complexity increases
Solution Approach 1:
The charge/discharge circuit is designed with multi-functionality: it can charge bit lines through charge transistors, discharge bit lines through discharge transistors, and cooperate with the sense amplifier circuit for both charging and discharging operations. This universal design allows a single circuit structure to perform multiple functions, reducing the need for separate dedicated circuits and thereby limiting the increase in device complexity.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a row direction and a column direction in a matrix shape; word lines which select the memory cell in the row direction; bit lines which select the memory cells in the column direction; a sense amplifier circuit which determines values stored in the memory cells based on states of the bit line; and a charge/discharge circuit which is formed in a well where the memory cell array is arranged and which charges or discharges the bit lines.