NAND Flash Memory Bit Line Segmentation for Power Reduction
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Solution Overview
Problem
NAND type flash memory devices face high power consumption and noise issues during write operations due to the large number of bit lines that need to be charged, leading to supply voltage drops and erroneous operations, especially as memory chip capacity increases and bit line length and capacitance grow.
Innovation Solution
The implementation of an even/odd (E/O) scheme in the control circuit, where either even-ordinal-number or odd-ordinal-number bit lines are selected for writing, while the other bit lines are set to a write-inhibiting voltage, reducing the number of bit lines requiring write voltage and minimizing the influence of adjoining channels, thereby reducing power consumption and threshold voltage distribution broadening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all bit lines are charged during write operation to enable simultaneous writing to multiple memory cells, then writing speed is improved, but power consumption and peak current increase significantly
Solution Approach 1:
The patent divides the bit lines into two separate groups: even-ordinal-number bit lines and odd-ordinal-number bit lines. By selecting only one group for writing at a time while setting the other group to write-inhibiting voltage, the patent segments the simultaneous write operation into sequential phases, reducing the number of active bit lines and thereby reducing power consumption and peak current requirements
2Productivity
If all bit lines are charged during write operation, then writing speed is improved, but noise increases causing supply voltage drop and erroneous operations
Solution Approach 1:
By segmenting bit lines into even and odd groups and activating only one group at a time, the patent reduces the total number of simultaneously charging bit lines. This segmentation directly reduces the cumulative noise and supply voltage drop that would occur if all bit lines were charged simultaneously, while still maintaining acceptable writing speed through sequential operations
3Adaptability or versatility
If voltage is applied to all bit lines during write operation, then write coverage is improved, but threshold voltage distribution broadening increases reducing data integrity
Solution Approach 1:
The patent segments the write operation to apply voltage to only one group of bit lines (even or odd) at a time, rather than all bit lines simultaneously. This reduces the number of adjoining channels influenced by the write operation, thereby minimizing threshold voltage distribution broadening in non-selected memory cells while maintaining comprehensive write coverage across all memory cells through sequential operations
Solution Approach 2:
The patent applies write-inhibiting voltage to one group of bit lines in advance before the write operation begins. This preliminary anti-action prevents voltage-induced threshold voltage shifts in memory cells connected to the non-selected bit lines, protecting data integrity in those cells while allowing the write operation to proceed on the selected bit lines
Data Source
AI summary
A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines; bit lines; and a control circuit configured to write multi-value data in the memory cells. The control circuit sets either even-ordinal-number bit lines or odd-ordinal-number bit lines as selected bit lines while setting the other as unselected bit lines; applies a write inhibiting voltage to the unselected bit lines; applies a write voltage to the selected bit lines corresponding to unwritten memory cells to be given one of threshold voltage distributions representing different written states; and applies the write inhibiting voltage to the selected bit lines corresponding to unwritten memory cells to be given any other of the threshold voltage distributions representing the different written states, memory cells already written, and memory cells to be maintained in a threshold voltage distribution representing an erased state, thereby executing a write operation.