NAND Flash Memory Bit Line Charging Voltage Control
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Solution Overview
Problem
As NAND flash memory cells are miniaturized, intercell interference due to capacitive coupling increases, leading to lower threshold voltages and reduced data retention, making it difficult to maintain reliable data storage and rewriting capabilities.
Innovation Solution
A nonvolatile semiconductor memory device with a bit line connected to a memory cell, a control circuit for verify operations, and a voltage setting circuit that adjusts the charging voltage for the bit line during write and read operations, using a verify operation with multiple threshold voltages to manage intercell interference and maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase storage capacity, then storage density is improved, but intercell interference due to capacitive coupling increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bit line charging voltage based on the operation mode (verify operation vs. read operation). During verify operations, a lower charging voltage is used to minimize intercell interference and accurately detect threshold voltage changes, while during read operations, a higher charging voltage is used to ensure proper data reading. This voltage parameter adjustment resolves the contradiction between miniaturization benefits and intercell interference drawbacks.
2Measurement precision
If verify operation uses low charging voltage to reduce intercell interference, then measurement precision is improved, but data retention may be compromised
Solution Approach 1:
The patent implements dynamics by making the bit line charging voltage variable rather than fixed. The charging voltage is dynamically selected based on the operation type: lower voltage during verify operations for precise measurement, and higher voltage during read operations for reliable data retrieval. This dynamic voltage adjustment allows the system to optimize for measurement precision when needed while maintaining data retention reliability through appropriate voltage levels during read operations.
3Manufacturing precision
If multiple verify operations with different threshold voltages are performed, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by varying the charging voltage parameter across multiple verify operations with different threshold voltages. This allows the control circuit to achieve precise threshold voltage control through voltage parameter adjustment rather than requiring complex additional circuitry. The voltage setting circuit modifies the charging voltage based on the specific verify operation requirements, enabling multiple threshold voltage levels to be tested while keeping the overall device structure relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces intercell interference, improves data retention, and enhances the reliability of NAND flash memory by adjusting the bit line charging voltage, allowing for accurate threshold voltage control and efficient data storage.
Implementation Method 1
the effect of intercell interference caused by capacitive coupling between adjacent cells has been becoming greater
Data Source
AI summary
A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.