NAND Flash Bit Line Pre-Charge Method for Peak Current Suppression
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Solution Overview
Problem
Conventional pre-charge methods in NAND flash memory devices result in prolonged sense time and high peak current during bit line pre-charging, which is detrimental for high-speed continuous page sensing in synchronization with external serial clock signals.
Innovation Solution
A pre-charge method that involves sequential activation of transistors using specific control signals to manage voltage supply and clamping, switching from low to high driving capability, and selectively disconnecting bit lines from virtual power to reduce peak current and shorten pre-charge time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional pre-charge methods are used to charge the bit line, then the bit line can be pre-charged, but the pre-charge time is prolonged and peak current is high
Solution Approach 1:
The pre-charge operation is divided into multiple phases with different driving capabilities. The voltage supply node switches from low driving capability to high driving capability at different timings for different bit lines, enabling faster pre-charge without excessive peak current. This segmentation of the pre-charge process into staged phases resolves the contradiction between pre-charge speed and sense time.
Solution Approach 2:
The driving capability of the voltage supply node is dynamically changed during the pre-charge operation. The system transitions from low driving capability to high driving capability at strategically timed moments, allowing the pre-charge process to adapt its speed requirements. This dynamic adjustment enables faster pre-charge when needed while controlling peak current, thereby reducing overall sense time.
2Power
If conventional pre-charge methods are used, then the bit line can be pre-charged, but peak current becomes excessively high
Solution Approach 1:
The pre-charge operation segments power delivery into multiple stages with different driving capabilities. By switching from low to high driving capability in phases rather than all at once, the system delivers necessary pre-charge power while avoiding simultaneous high-current draws that create excessive peak current. This staged power delivery resolves the contradiction between maintaining adequate pre-charge power and suppressing peak current.
Solution Approach 2:
The voltage supply node employs periodic switching between low and high driving capabilities during the pre-charge sequence. Different bit lines receive high driving capability at different periodic intervals rather than simultaneously, which maintains adequate pre-charge power delivery while distributing peak current demands over time. This periodic action pattern resolves the power versus peak current contradiction.
Data Source
AI summary
A semiconductor storing apparatus capable of suppressing a peak current in a pre-charge operation and shortening a sense time is provided. A pre-charge method of a bit line of an NAND type flash memory includes: turning on a transistor (BLPRE) and supplying a pre-charge voltage to a sense node (SNS) at time (t1); turning on a transistor (BLCLAMP) connected to the sense node (SNS) and used for generating a clamp voltage and turning on a transistor (BLCN) connected to a node (BLS) at time (t2), turning on a transistor (BLSe/BLSo) connected between the node (BLS) and a bit line (GBLe/GBLo) at time (t3), and performing the pre-charge operation on the bit line.