NAND Flash Block Copy via Segmented Bit Line Switching

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Solution Overview

Problem

Existing NAND FLASH memory devices with Shielded Bit Line (SBL) architecture face limitations in block copy performance due to sequential access of bit lines, resulting in slower page program and read times compared to All Bit Line (ABL) architecture.

Innovation Solution

Implementing multiple memory portions with a switching device between them and using multiple dynamic data caches (DDCs) to operate each portion independently, allowing concurrent data input/output and programming operations, which reduces bit line length and associated charging times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If Shielded Bit Line (SBL) architecture is used, then device complexity is reduced, but block copy performance and page program/read times deteriorate

Engineering Contradiction:

Improvebit line architecture complexityVSAvoidblock copy performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The memory device is divided into multiple memory portions (first portion and second portion) that can be independently accessed. This segmentation allows concurrent operations on different portions, improving block copy performance without requiring the more complex ABL architecture across the entire device.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A switching device is introduced as an intermediary between memory portions to enable selective coupling and uncoupling of bit lines. This mediator allows the system to achieve ABL-like performance by dynamically configuring bit line connectivity while maintaining the simpler SBL architecture foundation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If sequential access of bit lines is used, then device complexity is reduced, but page program and read times increase

Engineering Contradiction:

Improvebit line access methodVSAvoidpage program and read times

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent enables continuous useful action by allowing concurrent page program and read operations across different memory portions. While one portion is being read, another portion can be programmed simultaneously, eliminating idle time and reducing overall operation duration.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The switching device provides dynamic reconfiguration of bit line connectivity, allowing the system to adapt between sequential and concurrent access modes based on operational requirements. This dynamic capability enables faster page program and read times by switching to concurrent access when beneficial.

Inventive Principle:

Principle #15Dynamics

3Productivity

If multiple memory portions with switching devices are implemented, then block copy performance is improved, but device complexity increases

Engineering Contradiction:

Improveblock copy performanceVSAvoidmemory portion configuration

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The switching device serves multiple functions: it couples bit lines between memory portions during block copy operations, isolates portions during concurrent operations, and enables flexible configuration for different access patterns. This multi-functionality justifies the added complexity by providing versatile operational capabilities.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Speed

If data lines are continuously coupled between memory portions, then data transfer speed is maintained, but power consumption increases

Engineering Contradiction:

Improvedata transfer speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The switching device preemptively uncouples data lines between memory portions when concurrent operations are initiated, preventing unnecessary charge accumulation and power consumption. This preliminary action eliminates harmful effects before they occur by isolating portions that don't need to communicate.

Inventive Principle:

Principle #9Preliminary anti-action

Data Source

PatentUS9159373B2Enhanced block copy

Publication Date: 2015.10.13 MICRON TECHNOLOGY INC

AI summary

Methods and apparatuses for an enhanced block copy. One embodiment is reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.