NAND Flash Memory Block Division for Erasing Stress
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Solution Overview
Problem
In NAND flash memory, memory cells vary in characteristics, leading to incomplete erasing operations and excessive stress on some cells during collective erasing, as not all cells can be erased by a single operation.
Innovation Solution
The nonvolatile semiconductor memory device employs a block dividing unit to divide memory blocks into smaller divisional blocks, allowing for individual erasing operations with a higher voltage on unselected word lines and subsequent verifying operations to ensure complete erasing, thereby preventing excessive stress on memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If collective erasing is performed on all memory cells in a block by increasing well voltage, then erasing operation is simplified and can be completed in a single operation, but some memory cells may not be completely erased due to characteristic variations while others receive excessive stress
Solution Approach 1:
The patent divides a block into multiple sub-blocks, and each sub-block is further divided into multiple groups. This segmentation allows different voltage conditions to be applied to different groups simultaneously, ensuring that memory cells with varying characteristics can all be completely erased while maintaining high productivity through parallel processing.
Solution Approach 2:
The patent applies different voltage conditions to different groups within sub-blocks. Specifically, selected word lines receive 0V while unselected word lines receive positive voltages (e.g., 5V or 10V), creating locally optimized erasing conditions for different memory cell groups. This local quality approach ensures complete erasing for all cell types without excessive stress on any single group.
2Ease of operation
If a single erasing voltage is applied to all memory cells, then the erasing process is simple to control, but memory cells with different threshold values cannot all be completely erased
Solution Approach 1:
The patent dynamically adjusts voltage conditions by dividing memory blocks into sub-blocks and groups, applying different voltages (0V and positive voltages) to selected and unselected word lines respectively. This dynamic voltage adjustment ensures complete erasing for memory cells with varying threshold values while maintaining manageable control complexity through systematic voltage assignment.
Solution Approach 2:
The patent changes the voltage parameter applied to word lines based on the group and selection status. By applying 0V to selected word lines and positive voltages (5V or 10V) to unselected word lines, the patent creates multiple voltage conditions that accommodate different memory cell threshold values, ensuring complete erasing while maintaining operational simplicity through rule-based voltage assignment.
3Reliability
If multiple erasing operations are performed to ensure complete erasing of all memory cells, then erasing completeness is improved, but the time required for erasing increases and excessive stress is applied to cells erased in early stages
Solution Approach 1:
The patent segments a block into multiple sub-blocks with multiple groups each, enabling parallel erasing operations. Different voltage conditions are applied to different groups simultaneously, ensuring complete erasing for all memory cell types in a single operation cycle, thus eliminating the need for multiple sequential erasing operations and reducing total erasing time.
Solution Approach 2:
The patent merges multiple erasing operations into a single parallel operation by simultaneously applying different voltage conditions to different groups within sub-blocks. This merging approach achieves complete erasing for all memory cells with varying characteristics in one operation, preventing excessive stress on early-erased cells while eliminating time loss from sequential operations.
Data Source
AI summary
A block dividing unit groups one-word lines into p groups, to divide a block into p divisional blocks. An erasing unit has an erasing operation performed on data stored in memory cells in a memory cell array, on a divisional block basis. An erasing verifying unit has an erasing verifying operation performed on memory cells subjected to the erasing operation, on a divisional block basis.