NAND Flash Block Erase via Selected Data Storage
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Solution Overview
Problem
NAND-type flash memory devices face inefficiencies in block erasure operations, requiring repeated selection and erasure of individual blocks, which prolongs the time needed for data rewrite and leads to accumulated unerased original blocks, especially during frequent rewrite operations.
Innovation Solution
The implementation of a selected block data storage section in the row decoder that alternately stores erasure block data and defective block data, enabling efficient multiple block erasure by treating all blocks as defective, thereby reducing the time required for erasure operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual blocks are selected and erased one by one, then erasure completeness is maintained, but erasure time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-storing block address data in the selected block data storage section before the erasure operation. This allows the system to quickly retrieve and process multiple block addresses without repeated selection overhead, thereby reducing erasure time while maintaining completeness through systematic processing of all stored addresses
Solution Approach 2:
The patent segments the erasure operation into two distinct phases: a selection phase where block addresses are stored in the selected block data storage section, and an execution phase where erasure is performed on all stored blocks simultaneously. This segmentation eliminates repeated selection overhead and enables parallel processing of multiple blocks
2Productivity
If multiple blocks are erased simultaneously, then erasure speed improves, but control complexity increases
Solution Approach 1:
The selected block data storage section serves multiple functions: it stores block addresses for simultaneous erasure operations, maintains address information across different operation cycles, and coordinates the erasure process for multiple blocks. This multi-functionality enables parallel erasure without requiring separate control mechanisms for each block
Solution Approach 2:
The selected block data storage section acts as an intermediary between the address decoding circuit and the erasure execution mechanism. It temporarily holds and manages multiple block addresses, allowing the system to process multiple blocks efficiently without direct complex interaction between the decoder and erasure circuits
3Productivity
If block erasure is performed frequently, then data rewrite performance improves, but unerased blocks accumulate
Solution Approach 1:
The patent enables continuous erasure processing by maintaining block address data in the selected block data storage section and systematically processing all stored addresses without interruption. This continuous action ensures that blocks are erased promptly after identification, preventing accumulation of unerased blocks while maintaining high rewrite performance
Data Source
AI summary
According to a nonvolatile semiconductor memory device of the present invention, an address decode section 130 is provided in a block address decode circuit provided in a row decoder of a NAND-type flash memory device. The address decode section 130 has a selected block data storage section 132 composed of a latch circuit, a set section 134, and a reset section 136. The reset section 136 is composed of two nMOS transistors. Thus, defective block data and selected block data to be subjected to a multiple block erasure can be alternately stored in accordance with an operation without causing a complicated circuit structure or an increased chip size.