NAND Flash Block Merge Using Dual Program Methods
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Solution Overview
Problem
NAND flash memory devices face performance degradation due to the inefficiency of block merge operations, which are necessary to manage invalid and valid pages across multiple blocks, leading to increased time and reduced overall performance.
Innovation Solution
Implementing a method that uses distinct program methods for normal operations and block merge operations, with different incremental step pulse voltages and sensing schemes, to efficiently merge blocks by writing merge target data from merge target blocks into a merge-performing block, thereby improving threshold voltage distributions and operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a block merge operation is performed by merging valid pages distributed in a plurality of blocks and erasing unnecessary invalid pages, then free blocks are obtained, but overall performance of the NAND flash memory device drastically decreases due to the time required for the block merge operation
Solution Approach 1:
The block merge operation is divided into two distinct program methods: a first program method for normal data writing operations, and a second program method specifically for block merge operations. This segmentation allows the block merge function to be optimized independently from normal write operations, enabling faster merge performance while maintaining normal operation efficiency.
Solution Approach 2:
Different program parameters are applied for the first program method and the second program method. The second program method uses optimized parameters specifically tuned for block merge operations, including different incremental step pulse voltages and sensing schemes, which significantly reduces the time required for merging blocks while ensuring data integrity.
2Productivity
If distinct program methods with different incremental step pulse voltages and sensing schemes are used for block merge operations, then the time required for merging is reduced and overall performance is improved, but device complexity increases
Solution Approach 1:
The memory device is designed to support multiple program methods within a single device architecture. The controller can selectively apply the first program method for normal operations and the second program method for block merge operations. This multi-functionality allows the device to maintain improved performance through optimized merge operations while managing complexity through a unified control structure that handles both methods.
Data Source
AI summary
In a method of merging blocks in a semiconductor memory device according to example embodiments, a plurality of data are written into one or more first blocks using a first program method. One or more merge target blocks that are required to be merged are selected among the one or more first blocks. A merge-performing block for a block merge operation is selected among the one or more first blocks and one or more second blocks. A plurality of merge target data are written from the merge target blocks into the merge-performing block using a second program method that is different from the first program method.