NAND Flash Boot Loader Direct Execution
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Solution Overview
Problem
The use of ROM or NOR flash memory for storing boot loader code is expensive, and conventional systems cannot execute instructions stored in NAND flash memory effectively due to lack of support for addressing individual bytes or instructions.
Innovation Solution
A system that detects a reset signal and retrieves a predetermined page of data from nonvolatile memory into a register for direct execution by the processor, allowing for execution in place without storing instructions in another memory, and enabling random access to any byte within the register.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ROM or NOR flash memory is used to store boot loader code, then the system can execute instructions directly from nonvolatile memory, but the cost increases significantly
Solution Approach 1:
The patent replaces expensive ROM or NOR flash memory with cheaper NAND flash memory for storing boot loader code. NAND flash is a more cost-effective nonvolatile memory technology that can serve the same boot execution function, thereby reducing manufacturing costs while maintaining the ability to execute boot instructions directly from nonvolatile memory.
Solution Approach 2:
The patent changes the memory technology parameter from traditional ROM/NOR flash to NAND flash. This parameter change enables cost reduction while still allowing direct execution of boot instructions from nonvolatile memory, resolving the contradiction between execution capability and manufacturing cost.
2Ease of manufacture
If NAND flash memory is used to store boot loader code, then the cost decreases, but conventional systems cannot address individual bytes or instructions for execution
Solution Approach 1:
The patent segments the NAND flash memory into pages, with each page containing multiple instructions that can be individually addressed. This segmentation allows the system to retrieve and execute specific instructions or sequences of instructions from NAND flash memory, enabling execution in place while maintaining ease of operation for instruction addressing.
Solution Approach 2:
The patent introduces a page buffer as an intermediary between the processor and NAND flash memory. The page buffer temporarily holds retrieved pages of data, allowing the processor to access and execute individual instructions or sequences from the buffered data. This intermediary enables efficient instruction addressing and execution from NAND flash memory without requiring the processor to directly manage the complex memory structure.
3Device complexity
If instructions are retrieved from NAND flash memory as complete pages, then the system can execute in place without additional memory, but random access to individual bytes becomes limited
Solution Approach 1:
The patent segments each page of NAND flash memory into smaller addressable units, allowing the system to retrieve and access specific portions of a page rather than requiring complete page transfers. This segmentation enables random access to individual bytes or words within a page while maintaining the execution in place architecture, thus improving ease of operation without significantly increasing device complexity.
Solution Approach 2:
The page buffer serves as an intermediary that holds complete pages retrieved from NAND flash memory. Once a page is loaded into the buffer, the processor can randomly access any byte or word within that buffered page, enabling efficient random access operations without requiring additional memory resources. This intermediary approach maintains the simple execution in place architecture while providing enhanced random access capability.
Data Source
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AI summary
A method for booting a computing device, the method comprising: detecting a reset signal by a non-volatile memory die that includes an internal controller, a register, and a non-volatile memory, wherein the non-volatile memory includes a plurality of pages of data; retrieving, by the internal controller, a predetermined page of data from the non-volatile memory responsive to detecting the reset signal, wherein each of the plurality of pages of data is retrieved from the non-volatile memory as a unit and the predetermined page of data includes at least one instruction for booting the computing device; storing, by the internal controller, the predetermined page of data into the register; fetching, by a host processor, the at least one instruction from the register using at least one simple read command, wherein the simple read command includes an address for randomly accessing locations within the predetermined page of data; executing the at least one instruction by the host processor; and fetching, by the host processor, a second page of data from the non-volatile memory using a read command, wherein the read command retrieves the second page of data, and wherein the second page of data is different from the predetermined page of data.