NAND Flash Memory Buffer Management for Random Write Optimization
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Solution Overview
Problem
NAND flash memory devices face inefficiencies in data write performance due to the need for block erasure and sequential writing, leading to increased write times and busy times when handling random logical addresses, while optimizing for one aspect often compromises sequential write speed.
Innovation Solution
A memory device with a nonvolatile memory and a controller that manages memory blocks by temporarily storing data in a buffer and writing to erased blocks regardless of logical addresses, using a page shift method to reduce data moving processes and implement a dual-sector coupling process to enhance write efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written sequentially in the same block, then write performance is maintained, but random logical address writes require frequent block erasures and data copying which increases write time
Solution Approach 1:
The memory device divides each memory block into multiple sectors, allowing independent write operations within sectors. This segmentation enables the system to write data to different sectors without requiring complete block erasure, thereby reducing write time while maintaining sequential write performance.
Solution Approach 2:
The controller pre-manages sector-level erase operations and data copying in advance, preparing erased sectors before actual data write operations. This preliminary action reduces the time required for random logical address writes by avoiding sequential block erasure and data copying operations.
2Quantity of substance
If block size is increased to increase capacity, then storage capacity improves, but inter-block data copying time prolongs and maximum moving time increases
Solution Approach 1:
By dividing large memory blocks into smaller sectors, the system reduces the amount of data that needs to be copied during erase and rewrite operations. This segmentation maintains large overall capacity while reducing the time required for inter-block data copying and maximum moving operations.
3Loss of time
If a data write process is used to shorten random logical address write time, then random write performance improves, but sequential logical address write speed decreases
Solution Approach 1:
The sector-based segmentation allows the system to optimize for random writes by operating at the sector level rather than block level, while maintaining sequential write speed through efficient sector-to-sector data transfer. This resolves the contradiction by enabling fast random access without compromising sequential performance.
Solution Approach 2:
The controller dynamically adjusts the write operation strategy based on the access pattern (random or sequential) and selects the appropriate sector or block for writing. This dynamic approach allows the system to optimize performance for the specific workload type while maintaining good performance across different access patterns.
Data Source
AI summary
A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.