NAND Flash Cache Programming for TLC Data In Time Reduction
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Solution Overview
Problem
In NAND flash memory systems, the data-in time in page buffers limits overall system write performance due to prolonged programming and verification of multiple bits per memory cell, necessitating optimization of cache programming to reduce data-in time without losing original programming data.
Innovation Solution
The method involves discarding previously programmed logic pages from data latches and uploading new programming data to cache latches, inhibiting memory cells from further programming, and recovering original data in case of failure by using read reference voltages to separate logic states and construct binary codes, specifically optimized for triple-level-cell (TLC) mode with 8 logic states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If original programming data are stored in page buffers throughout the entire write operation to prevent data loss, then data reliability is improved, but data-in time increases and limits overall system write performance
Solution Approach 1:
The patent applies the discarding and recovering principle by selectively discarding verified programming data from page buffers while maintaining recovery capability through inhibit information storage. Once data is successfully programmed and verified in memory cells, the corresponding page buffer content can be discarded or overwritten with new data, yet the system retains the ability to recover original data if needed through the inhibit mechanism. This resolves the contradiction by reducing data-in time while preserving data reliability through controlled data lifecycle management.
2Quantity of substance
If multiple bits per memory cell are programmed to increase storage capacity, then storage density is improved, but programming and verification time is prolonged
Solution Approach 1:
The patent applies segmentation by dividing the programming operation into distinct phases: programming first logic states, verifying those states, then programming second logic states. This segmented approach allows the system to manage multi-bit programming in manageable stages, reducing the overall programming and verification time while maintaining high storage capacity through multi-level cell operation.
3Productivity
If data-in time in page buffers is reduced to improve write performance, then productivity is improved, but risk of data loss increases
Solution Approach 1:
The patent applies preliminary action by pre-programming first logic states and verifying them before proceeding to program second logic states. This preliminary verification ensures data integrity early in the process, allowing the system to reduce data-in time and improve write performance while maintaining data safety through staged verification and the inhibit information mechanism that protects against data loss.
Data Source
AI summary
A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.