Caching Device for NAND Flash Address Translation
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Solution Overview
Problem
The existing NAND flash memory management techniques, particularly the block-level mapping mechanism, are inefficient in mapping logical addresses to physical flash memory addresses, leading to slow read and write access speeds due to the need to search through pages within a block, which affects overall performance.
Innovation Solution
A caching device is introduced between the memory read/write controller and the flash memory, comprising an instruction register, logical address register, data register, auxiliary controllers, microprocessor, address translation unit, caching control unit, and caching instruction/data buffer area, utilizing a search tree for efficient logical to physical address translation, enhancing caching operations and reducing RAM usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If block-level mapping mechanism is used to maintain address translation table, then RAM space requirement is reduced, but address translation efficiency deteriorates due to the need to search through pages within a block
Solution Approach 1:
The patent segments the address translation mechanism into two parts: a search tree structure for efficient logical-to-physical address translation and a block-level mapping mechanism for maintaining the translation table. The search tree is divided into multiple levels with each level handling a specific portion of the address space, allowing fast translation without searching through entire blocks.
Solution Approach 2:
The patent introduces a new dimensional approach by using a search tree structure that organizes address translations in a hierarchical manner rather than linearly. This multi-level search tree allows the system to translate addresses by traversing multiple dimensions (levels) simultaneously, significantly improving translation efficiency while maintaining compact RAM usage.
2Quantity of substance
If block-level mapping mechanism is used, then RAM space is saved, but read and write access speed decreases due to time-consuming page search operations
Solution Approach 1:
The patent implements preliminary action by pre-building and maintaining a search tree structure that contains translation information for multiple address ranges. When a read or write operation occurs, the system can directly query the search tree for the required physical address without performing time-consuming search operations through entire blocks, thus speeding up access while using minimal RAM.
Solution Approach 2:
The search tree structure serves as an intermediary between the logical address space and the physical flash memory addresses. It mediates the translation process by providing fast lookup capability, allowing the system to avoid direct block-level searching and significantly improve read/write speeds without requiring large amounts of RAM.
3Adaptability or versatility
If conventional address translation technique is used, then existing file system compatibility is maintained, but mapping efficiency deteriorates due to linear search through blocks
Solution Approach 1:
The patent achieves universality by designing a caching device that maintains compatibility with existing file systems while introducing advanced address translation capabilities. The device can work with conventional file systems like FAT16/32 and NTFS while simultaneously providing fast address translation through the search tree mechanism, thus maintaining versatility without sacrificing mapping efficiency.
Solution Approach 2:
The patent creates a copy of the address translation function using a search tree structure that mirrors the logical address space organization. This copied structure allows for efficient translation without altering the existing file system interface, enabling the system to maintain compatibility while achieving superior mapping performance through the replicated but optimized translation mechanism.
Data Source
AI summary
A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.