Parallel NAND Flash Write-RX Calibration via Transformation Matrix
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Solution Overview
Problem
Current NAND flash devices require lengthy Write-RX calibration processes, particularly during SSD power-up, which slows down the availability of SSDs for use after powering up, due to serial determination of pass/fail information for DQ pins using trim settings.
Innovation Solution
A calibration circuit that applies 16 trim codes to DQ pins to determine pass/fail results in parallel using a transformation matrix, allowing for simultaneous determination of trim settings for all pins, thereby accelerating the Write-RX training sequence and reducing the SSD power-up time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If serial determination of pass/fail information is used for DQ pins using trim settings, then measurement precision is maintained, but productivity deteriorates due to lengthy calibration time
Solution Approach 1:
The patent segments the calibration process by dividing DQ pins into multiple groups and applying different trim settings to each group simultaneously. This allows parallel processing of multiple pins through segmentation, maintaining measurement precision while significantly improving calibration productivity.
Solution Approach 2:
The patent introduces a new dimension to the calibration process by using multiple trim settings across different pin groups simultaneously. Instead of sequential single-pin calibration, the system calibrates multiple pins in parallel by adding the trim setting dimension, thereby improving productivity without sacrificing precision.
2Productivity
If parallel determination of pass/fail information is used for DQ pins using trim settings, then productivity is improved by accelerating calibration, but device complexity increases due to transformation matrix requirements
Solution Approach 1:
The patent merges multiple calibration operations into a single unified transformation matrix structure. By combining the pass/fail determination logic for multiple pin groups into one matrix operation, the system achieves parallel calibration (improving productivity) while managing complexity through consolidation rather than proliferation of separate circuits.
Solution Approach 2:
The transformation matrix serves multiple functions simultaneously: it determines pass/fail status for multiple pin groups, applies different trim settings, and enables parallel calibration operations. This multi-functionality improves productivity while containing device complexity by using a single versatile mathematical structure.
3Productivity
If 16 trim codes are applied to all DQ pins simultaneously, then productivity is improved by parallel processing, but loss of time increases due to the complexity of determining pass/fail information
Solution Approach 1:
The patent performs preliminary organization of trim codes by grouping them and assigning to different pin groups before the actual calibration measurement. This preliminary arrangement enables the transformation matrix to process all 16 trim codes in parallel without sequential overhead, improving productivity while minimizing the time lost to determination complexity.
Data Source
AI summary
In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.