NAND Flash Memory Read Voltage Control for Capacitive Coupling Noise
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Solution Overview
Problem
In NAND-type flash memory devices, the integration and capacity advancements lead to issues with precise threshold distribution setting for multi-level data storage, and there is a risk of erroneous erase-verify due to capacitive coupling noise, causing cells to be incorrectly judged as erased despite insufficient erasure.
Innovation Solution
Implementing a data read mode with specific bias conditions, including applying a selected word line with a read voltage and unselected word lines with lower read pass voltages, and optionally using dummy cells to mitigate capacitive coupling effects, ensuring accurate data read operations even with uncertain erase states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cells are connected in series to achieve high integration and capacity, then device capacity and integration are improved, but capacitive coupling noise increases causing erroneous erase-verify judgments
Solution Approach 1:
The patent segments the word lines into different voltage control groups: selected word lines receive high voltage for data programming, while unselected word lines receive low voltage to suppress capacitive coupling noise. This segmentation allows high-capacity NAND strings to operate without erroneous verify judgments caused by noise
Solution Approach 2:
Different voltage levels are applied to different word lines based on their functional role. The selected word line receives programming voltage (e.g., 20V) while unselected word lines receive suppressed voltage (e.g., 0V or low voltage), creating local quality differentiation that eliminates noise interference in non-programmed cells
2Power
If high voltage is applied to selected word line for data programming, then data write capability is improved, but capacitive coupling to unselected word lines causes erroneous erase-verify judgments
Solution Approach 1:
Before applying high programming voltage to the selected word line, the patent preemptively applies low voltage to unselected word lines to counteract the upcoming capacitive coupling effect. This preliminary anti-action prevents the noise from causing erroneous verify judgments
Solution Approach 2:
The patent dynamically changes voltage parameters during operation: unselected word lines are held at low voltage during programming to suppress noise, then voltage levels are adjusted appropriately during verify operations to ensure accurate threshold voltage detection without capacitive coupling interference
3Speed
If unselected word lines are held at high voltage during read operations, then read speed is improved, but capacitive coupling from selected word line causes threshold voltage detection errors
Solution Approach 1:
During read operations, the patent applies different voltage levels to different word lines: the selected word line receives read voltage while unselected word lines receive suppressed voltage. This local quality differentiation prevents capacitive coupling from affecting threshold voltage detection in unselected cells
Solution Approach 2:
The patent dynamically adjusts word line voltages based on operational phase: during programming, unselected word lines are suppressed; during reading, voltage levels are changed to enable fast read while maintaining detection precision. This dynamic adaptation resolves the contradiction between speed and precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise data read operations without being influenced by the precision of the erase-verify conditions, ensuring accurate data retrieval and preventing erroneous judgments due to capacitive coupling noise, even in high-capacity NAND-type flash memory devices.
Implementation Method 1
a memory cell in the NAND-type flash memory has a charge storage layer (e.g., floating gate) formed on a semiconductor substrate with a tunnel insulating film interposed therebetween
Implementation Method 2
Data write is performed by applying program or write voltage Vpgm to a selected word line, thereby injecting electrons into the floating gate from the cell channel with FN tunneling current
Implementation Method 3
the selected cell's channel is boosted in potential by capacitive coupling from the selected word line, so that electron injection into the floating gate will be inhibited
Data Source
AI summary
A memory device including a NAND string with multiple memory cells connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the device has a data read mode performed under the bias condition of: a selected cell is applied with a read voltage; and unselected cells are applied with read pass voltages, and wherein in the data read mode, one of the unselected cells adjacent to one of the first and second select gate transistor is applied with a first read pass voltage while the other unselected cells are applied with a second read pass voltage lower than the first read pass voltage.