NAND Flash Memory Cell Programming via Sequential Data Line Connection
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Solution Overview
Problem
Programming operations in NAND flash memory devices are power-intensive and time-consuming due to the need to sequentially connect memory cells to data lines and apply programming voltages, which increases power consumption and reduces throughput.
Innovation Solution
The solution involves a method where memory cells are connected to data lines sequentially while applying a program voltage, allowing for efficient programming by controlling the select transistors and access lines to minimize power usage and optimize programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are connected sequentially to data lines while applying program voltage, then programming throughput is improved, but power consumption increases
Solution Approach 1:
The memory array is divided into multiple banks, and programming operations are segmented across different banks. Multiple memory cells from different banks can be programmed simultaneously by connecting them to different data lines in parallel, thereby improving throughput while distributing power consumption across multiple independent operation segments.
Solution Approach 2:
Memory cells are pre-charged to a first voltage level before programming begins. This preliminary action prepares the cells for rapid programming by establishing the initial electrical state, allowing the programming operation to proceed more efficiently with reduced overall power requirements since less voltage transition is needed during the actual programming phase.
2Speed
If programming voltage is applied to multiple memory cells simultaneously, then programming speed is improved, but difficulty of controlling voltage distribution increases
Solution Approach 1:
The memory array is divided into multiple banks with separate data line connections. This segmentation allows independent voltage control for each bank, simplifying the distribution and monitoring of programming voltages while enabling simultaneous programming operations across multiple segments at controlled voltage levels.
Solution Approach 2:
Sense amplifiers are used as intermediary components between the data lines and memory cells. These sense amplifiers facilitate controlled voltage distribution by acting as buffer stages that can precisely manage voltage transitions and maintain stable voltage levels during simultaneous programming operations across multiple memory cells.
3Use of energy by moving object
If sequential connection method is used for programming, then power consumption is reduced, but programming time increases
Solution Approach 1:
The memory system is divided into multiple independently controllable banks that can operate in parallel. This segmentation enables the system to perform sequential-like low-power operations within each bank while simultaneously processing multiple banks, effectively achieving both low power consumption and reduced total programming time through parallelized segmented operations.
Solution Approach 2:
The system dynamically switches between different operating modes: it can perform rapid simultaneous programming when power availability permits, and switch to sequential low-power mode when power conservation is prioritized. This dynamic adaptability allows optimization of the trade-off between programming speed and power consumption based on real-time system conditions.
Data Source
AI summary
Programming methods include programming first and second data in first and second memory cells, reading the first data from the first memory cell by applying a read voltage to an access line connected to the first and second memory cells while the first memory cell is electrically connected to a data line and while the second memory cell is electrically disconnected from the data line, reading the second data from the second memory cell by electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line while the read voltage remains applied to the access line, and programming the read first data and the read second data in a single memory cell connected to a different access line.