NAND Flash Memory Cell Size Variation for Program Speed Uniformity

The patent applies local quality by differentiating the size of memory cells based on their position within the string. Specifically, first and last memory cells (connected to source and drain select transistors) are designed with a larger area than intermediate memory cells. This local differentiation compensates for the interference effect experienced only by end cells, thereby restoring program speed uniformity across the entire string while maintaining high integration density through the series connection structure.

Rather than uniformly increasing the size of all memory cells in the string, the patent applies local quality by enlarging only the first and last memory cells that are affected by select transistor interference. Intermediate memory cells maintain their original smaller size. This selective approach achieves program speed uniformity while minimizing the overall area increase compared to a uniform size increase across all cells.

The patent resolves this contradiction by applying local quality - making the size of memory cells position-dependent. First and last memory cells are enlarged to compensate for the harmful interference from source and drain select transistors, while intermediate cells maintain a smaller uniform size. This creates a size pattern such as: larger, smaller, smaller, ..., smaller, larger, which optimizes both area utilization and program speed uniformity across the string.