NAND Flash Memory Channel Grounding for Program Interrupts
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Solution Overview
Problem
NAND Flash memory devices experience issues with hole accumulation during program operation suspension or termination due to floating channels, leading to increased threshold voltages and fail bit counts, which affect subsequent read operations.
Innovation Solution
The solution involves turning on the drain select gate (DSG) and/or source select gate (SSG) transistors to ground the channel, applying a pass voltage to release accumulated holes, thereby preventing false increases in threshold voltage and reducing fail bit counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the program operation is suspended or terminated during NAND Flash memory device operation, then the memory device can respond to interrupt commands and perform other operations, but hole accumulation occurs in the floating channel leading to increased threshold voltages and fail bit counts
Solution Approach 1:
The patent applies preliminary action by grounding the channel through DSG/SSG transistors before the program operation is suspended or terminated. This preventive measure removes holes from the channel in advance, preventing the accumulation problem that would otherwise occur during suspension. The channel is placed in a known good state (grounded) before the interrupt occurs, ensuring reliability is maintained despite the suspension.
2Reliability
If the program operation continues without suspension, then memory device performance is maintained, but the device cannot respond to interrupt commands or perform other operations
Solution Approach 1:
The patent prepares the channel by grounding it through DSG/SSG transistors before suspension is needed. This preliminary grounding action ensures that when the interrupt occurs, the channel is already in a safe state without accumulated holes, allowing the device to suspend operations and respond to interrupts without compromising future read operations.
3Productivity
If the channel is left floating during program operation suspension, then the memory device can be suspended efficiently, but false increases in threshold voltage occur leading to increased fail bit counts
Solution Approach 1:
The patent applies preliminary grounding action through DSG/SSG transistors before the program operation is suspended. This ensures the channel is in a controlled state (grounded) rather than floating, preventing false threshold voltage increases while still allowing efficient suspension. The grounding is established in advance, so when suspension occurs, the channel remains controlled.
Solution Approach 2:
The patent converts the potentially harmful floating channel state into a beneficial grounded state by using DSG/SSG transistors to deliberately ground the channel before suspension. This intentional grounding transforms what would be a harmful condition (floating channel causing hole accumulation) into a controlled, beneficial condition (grounded channel preventing accumulation), especially when interrupts occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces fail bit counts and improves memory device performance by avoiding hole accumulation during program operation suspension or termination.
Implementation Method 1
turning on the drain select gate (DSG) and/or source select gate (SSG) transistors to ground the channel
Data Source
AI summary
A memory device includes a memory string including a first select gate transistor and memory cells, and a peripheral circuit coupled to the memory string and configured to, during a program operation on a first memory cell of the memory cells, apply a program voltage to a first word line coupled to the first memory cell, receive an interrupt signal, and in response to the interrupt signal, after applying the program voltage to the first word line, apply a first voltage to a first select line coupled to the first select gate transistor. The first voltage is greater than a threshold voltage of the first select gate transistor.