NAND Flash Charge Pump Word Line Short Detection

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Solution Overview

Problem

Memory devices face defects such as word line and bit line shorts, which can occur during manufacturing or over time, leading to operational failures and requiring improved testing methods to detect these defects effectively.

Innovation Solution

Implementing a charge pump circuit with a regulator and current sensing mechanisms to monitor voltage and duty cycle, allowing for real-time detection of word line shorts by tracking the activity of the control signal and counting clock cycles, thereby identifying defects in memory arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional manufacturing testing is used, then manufacturing process is simple, but defects like word line shorts remain undetected

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtesting mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory device performs self-diagnosis by using its own charge pump and control logic to detect defects in its word lines and bit lines, eliminating the need for external testing equipment and reducing overall system complexity

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The defect detection mechanism uses feedback from charge pump current measurements and control signal monitoring to identify defects, allowing the system to adaptively respond to detected issues and improve reliability

Inventive Principle:
Principle #23Feedback

2Reliability

If real-time defect detection is implemented, then operational reliability improves, but device complexity increases

Engineering Contradiction:
Improveoperational reliabilityVSAvoidmonitoring circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The charge pump circuit serves multiple functions: it generates necessary voltages for memory operation and simultaneously acts as a sensing mechanism for defect detection, reducing the need for separate dedicated testing circuits

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The defect detection functionality is merged with the existing charge pump and control logic, combining voltage generation and defect monitoring into a unified circuit architecture that minimizes additional complexity

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If comprehensive defect monitoring is performed, then defect detection precision improves, but processing time increases

Engineering Contradiction:
Improvedefect detection precisionVSAvoiddetection processing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The defect detection operates continuously during normal memory operations rather than requiring separate testing phases, allowing real-time monitoring without significant time loss and maintaining high detection precision

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system performs preliminary defect detection during manufacturing and initialization phases, identifying and marking defective lines before full operation begins, which prevents time loss during active use

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient detection of word line shorts and other defects, preventing operational failures and allowing for timely recovery or exclusion of defective memory planes, thus enhancing the reliability and performance of memory systems.

Implementation Method 1

determining whether a quantity of current generated by the pump circuit is greater than a specified threshold current

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11710533B2NAND flash array defect real time detection
Publication Date: 2023.07.25 MICRON TECHNOLOGY INC
  • US11710533B2 patent drawing
  • US11710533B2 patent drawing
  • US11710533B2 patent drawing

AI summary

A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.