NAND Flash Dual-Code Architecture for Chipkill Error Recovery
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Solution Overview
Problem
NAND Flash storage systems face challenges in providing adequate error protection and recovery techniques without requiring additional hardware, particularly in scenarios involving random errors and chip failures.
Innovation Solution
Implementing a dual error correction code system, where a first error correction code is used for initial decoding attempts, and a second error correction code is employed when the first code fails, with the second code providing parity information stored on a redundant NAND Flash chip for enhanced error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAID type solution with additional NAND Flash chip is used for chipkill protection, then data recovery capability is improved, but hardware cost and system complexity increase
Solution Approach 1:
The error correction capability is segmented into two independent codes: a first error correction code applied to individual data sets stored on separate chips, and a second error correction code applied across multiple data sets. This segmentation allows each code to handle specific error scenarios independently, achieving comprehensive protection without requiring additional hardware beyond the existing Np+1 chip configuration.
Solution Approach 2:
The patent combines two different error correction codes with complementary strengths into a unified error correction system. The first code (e.g., BCH or Reed-Solomon) handles errors within individual data sets, while the second code (e.g., LDPC or Turbo code) handles errors across multiple data sets including chipkill scenarios. This composite coding approach achieves enhanced reliability without additional hardware.
2Reliability
If stronger error correction is implemented to handle random errors, then error protection capability is improved, but processing complexity and time increase
Solution Approach 1:
The error correction system dynamically selects which code to apply based on the error scenario. For typical random errors within a single chip, only the first error correction code is applied. For chipkill scenarios affecting multiple chips, the second error correction code is applied to the remaining data sets. This dynamic adaptation optimizes decoding time by avoiding unnecessary processing while maintaining comprehensive error protection.
Solution Approach 2:
The patent applies error correction in stages: first attempting correction with the first code on individual data sets, then selectively applying the second code only when needed for chipkill recovery. This partial action approach avoids the excessive processing time that would result from always applying the strongest possible error correction to all data, while still providing adequate protection for all error scenarios.
Data Source
AI summary
A first decoder performs decoding on each data set in a first plurality of data sets using a first code; each data set in the first plurality is stored on a different NAND Flash chip. It is determined if the first decoding is successful; if not, a second decoder performs a second decoding on each data set in a second plurality of data sets using a second code; each data set in the second plurality includes at least some data, after the first decoding using the first code, from each data set in the first plurality. The first decoder performs a third decoding on each data set in the first plurality using the first code, where each data set in the first plurality includes at least some data, after the second decoding using the second code, from each data set in the second plurality.