NAND Flash ECC Layout Using Cross-Page Column Parity
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Solution Overview
Problem
NAND flash memory's error correction capability is limited due to the restricted parity area in pages, which hampers the efficient management and correction of data errors.
Innovation Solution
The implementation of a memory system with a first, second, and third error correction part, where parity data is generated in both the row and column directions, utilizing a redundant area in the MLC area to enhance error correction capabilities by storing column parity data, allowing for error detection and correction across pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity data is stored in the same page as user data, then error correction can be performed, but the parity area is limited and error correction capability is restrained
Solution Approach 1:
The patent extends error correction from a single-page (2D) structure to a multi-page (3D) structure by generating parity data across multiple pages in the column direction. This dimensional extension allows the system to utilize redundant areas across multiple pages rather than being confined to the limited parity area within a single page, thereby improving error correction capability without increasing the parity area within each individual page.
2Reliability
If more parity data is generated to improve error correction, then reliability increases, but storage space is consumed
Solution Approach 1:
The patent recovers and utilizes the redundant area that would otherwise be wasted or unused in MLC memory pages. By generating column parity data that spans multiple pages and storing it in these redundant areas, the system effectively recovers unused storage space and converts it into functional parity data, thereby improving error correction capability without consuming additional storage resources.
Data Source
AI summary
According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.