NAND Flash Memory Command-Based Interface Pin Reduction
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Solution Overview
Problem
Conventional NAND flash memory devices require multiple control pins for asynchronous control interfaces, which increases cost and size, limiting their usage due to pin-related constraints.
Innovation Solution
Implementing a command-based interface in NAND flash memory integrated circuits that reduces the number of pins needed by using a shared set of I/O lines for commands, addresses, and data, with a reset or start pin to maintain synchronization, eliminating the need for separate pins for signals like Read/Write and Address Enable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional asynchronous control interface with separate control pins (ALE, CLE, RE) is used, then reliable data transfer control is achieved, but device size and cost increase due to additional pins
Solution Approach 1:
The patent merges multiple separate control signals (ALE, CLE, RE) into a single shared control line that multiplexes between different control functions. The control line alternates between latching addresses, latching commands, and enabling reads/writes based on timing sequences, thereby reducing the number of pins while maintaining control reliability.
Solution Approach 2:
The shared control line performs multiple functions at different times: it acts as an address latch enable signal, a command latch enable signal, and a read/write enable signal. This multi-functional approach eliminates the need for dedicated pins for each control function, reducing device footprint while preserving comprehensive control capability.
2Ease of operation
If separate control pins for ALE, CLE, and RE are implemented, then precise control of read/write operations is achieved, but manufacturing cost increases due to additional pins
Solution Approach 1:
The patent combines multiple control functions into a single pin that is time-multiplexed. The control line is sequentially activated for different purposes based on the command cycle timing, eliminating the need for separate pins for address latching, command latching, and read/write enabling, thereby reducing manufacturing cost while preserving operational precision.
3Adaptability or versatility
If multiple control pins are used for asynchronous interface, then complete control functionality is achieved, but device complexity increases
Solution Approach 1:
The shared control line is designed to perform multiple control functions through temporal separation. By carefully timing the activation of the control line for different purposes (address latching, command latching, read enable, write enable), the system achieves complete control functionality with a single pin, thereby reducing interface complexity while maintaining full adaptability.
Data Source
AI summary
Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce the number of pins that are needed on each integrated circuit, and therefore reduce the cost and size of those integrated circuits. In some embodiments, an on-die cache buffer may be used to buffer data transfers between a high-speed memory bus and the slower speed non-volatile array.