NAND Flash Memory Concurrent Operation Control
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Solution Overview
Problem
Conventional methods for operating multiple NAND flash memory chips stacked in a package require sequential completion of operations, leading to prolonged program, erase, or read times as each chip is driven only after the previous one has finished.
Innovation Solution
A method where operation commands and addresses are sequentially applied to NAND flash memory chips without waiting for the previous chip's operation to complete, checking completion times, and adjusting addresses as necessary to ensure simultaneous operation across all chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sequential operation method is used for multiple NAND flash memory chips, then operation simplicity is maintained, but overall operating time increases significantly
Solution Approach 1:
The memory controller applies operation commands and addresses to multiple flash memory chips in advance, before previous operations complete. This preliminary action enables overlapping of operations across different chips, reducing total operating time while maintaining simple sequential command application structure
Solution Approach 2:
The system continuously applies operations to different flash memory chips without idle waiting periods. When one chip completes its operation, the controller immediately transitions to checking completion status of other chips or applying new commands, ensuring continuous productive action and eliminating wasted time
2Reliability
If sequential completion method is used for program operations, then data integrity is ensured, but program time increases
Solution Approach 1:
The system divides the flash memory storage into multiple independent chips that can operate simultaneously. Each chip handles specific data segments, allowing parallel program operations across different chips while maintaining data integrity through proper address management and completion checking
Solution Approach 2:
The memory controller continuously monitors operation completion status of each flash memory chip through feedback signals. This feedback mechanism ensures that operations are properly coordinated and data integrity is maintained while enabling faster overall program time through parallel processing
3Device complexity
If one chip is driven at a time, then control complexity is low, but productivity decreases
Solution Approach 1:
The system merges multiple flash memory chips into a single controlled unit managed by one memory controller. This combining approach maintains low control complexity while significantly improving productivity by enabling simultaneous operations across multiple chips through coordinated command application and completion monitoring
Data Source
AI summary
A method of operating a packaged flash memory module includes applying a first program or erase command and a first address associated with the first commend to a first flash memory chip of a plurality of flash memory chips that are arranged within the packaged flash memory module; applying a second program or erase command and a second address associated with the second commend to a second flash memory chip of the plurality of flash memory chips that are arranged within the packaged flash memory module, the second command being applied to the second flash memory chip prior to the completion of the first command by the first flash memory chip; and determining whether or not the first flash memory chip has completed the first command.