NAND Flash Memory Concurrent Page Programming
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Solution Overview
Problem
NAND flash memory devices are limited by their sequential programming approach, which restricts data programming speed and efficacy, making them unsuitable for fast data operations in portable electronic applications.
Innovation Solution
Implementing a NAND flash memory device that allows concurrent programming operations across multiple pages with limited die area penalty and small external RAM overhead, using capacitive storage elements to temporarily store program information and enable simultaneous programming of cells without interrupting existing write cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential programming approach is used in NAND flash memory, then device complexity is reduced, but programming speed deteriorates
Solution Approach 1:
The patent segments the bit line into multiple independent segments, each capable of simultaneous programming operations. This allows multiple programming operations to occur in parallel across different segments, dramatically increasing programming speed while maintaining manageable device complexity through modular organization
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory cells into multiple pages that can be programmed simultaneously. By adding this temporal and spatial dimension to the programming process, the system achieves faster overall programming without proportionally increasing device complexity
2Productivity
If multiple pages are programmed concurrently, then programming speed is improved, but die area increases
Solution Approach 1:
The patent merges multiple bit line segments into a shared infrastructure with common control logic and capacitive storage elements. This consolidation allows concurrent programming of multiple pages while using shared resources, achieving high programming throughput without proportionally increasing die area
Solution Approach 2:
The patent creates universal control mechanisms and shared capacitive storage elements that serve multiple pages simultaneously. These multi-functional components enable concurrent programming operations across different pages without requiring dedicated resources for each page, thus improving productivity while controlling die area
3Productivity
If concurrent programming operations are implemented, then data storage efficiency is improved, but external RAM usage increases
Solution Approach 1:
The patent implements self-service capacitive storage elements integrated directly within the flash memory device that temporarily hold programming data during concurrent operations. This internal storage mechanism eliminates the need for external RAM to buffer data during programming, improving data storage efficiency while minimizing external RAM usage
Solution Approach 2:
The patent introduces capacitive storage elements as intermediary components between the programming interface and the memory cells. These intermediaries temporarily hold programming data and enable concurrent programming operations without requiring external RAM, thus improving productivity while reducing external memory requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster program speeds and efficient data storage by allowing concurrent programming of multiple cells, reducing the time required for data operations and minimizing external RAM usage, thus enhancing the performance of NAND flash memory in portable devices.
Implementation Method 1
using capacitive storage elements to temporarily store program information and enable simultaneous programming of cells
Implementation Method 2
the high program voltage applied to the gate of cell 1201 to induce electron tunneling onto the floating gate of the cell 1201
Data Source
AI summary
A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line.