Configurable NAND Flash Interface for Bonding and Speed Trade-offs

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Solution Overview

Problem

Conventional NAND flash memory systems face challenges in efficiently communicating between NAND flash memory chips and controllers due to the inflexibility of simple parallel interfaces, which limits data transfer rates and increases bonding complexity and costs.

Innovation Solution

A NAND flash memory chip with a configurable interface that can switch between parallel and serial modes, reducing the number of data and control channels, and utilizing Double Data Rate (DDR) communication to maintain high data transfer rates, even in serial mode, with a clock frequency of at least 200 Megahertz for data transfer rates of at least 50 Megabytes per second.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a simple parallel interface is used to connect NAND flash memory chips and controllers, then the connection is straightforward and compatible with legacy systems, but the data transfer rate is limited and bonding complexity increases

Engineering Contradiction:

Improveinterface compatibilityVSAvoiddata transfer rate

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The interface is designed to dynamically switch between parallel and serial modes based on the specific application requirements. The configurable interface allows the system to adapt the communication mode (parallel or serial) according to performance needs, bonding complexity constraints, and compatibility requirements, thereby resolving the contradiction between versatility and productivity

Inventive Principle:

Principle #15Dynamics

2Device complexity

If a simple parallel interface is used for NAND flash memory communication, then the interface structure is straightforward, but the number of bonding wires and bonding operations increases

Engineering Contradiction:

Improveinterface structureVSAvoidbonding complexity

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

The interface configuration allows dynamic selection between parallel and serial modes, enabling the system to optimize for manufacturing ease when needed. In serial mode, fewer bonding wires and fewer bonding operations are required, directly addressing the contradiction between interface structure simplicity and manufacturing ease

Inventive Principle:

Principle #15Dynamics

3Ease of manufacture

If serial mode is used to reduce the number of data channels, then bonding complexity is reduced, but data transfer rates are compromised unless high speed Double Data Rate communication is used

Engineering Contradiction:

Improvebonding complexityVSAvoiddata transfer rate

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The interface employs parameter changes by implementing high speed Double Data Rate (DDR) communication in serial mode, where the data transfer rate is doubled relative to the clock frequency. This allows the system to maintain high productivity (data transfer rates of at least 50 Megabytes per second with 200 Megahertz clock frequency) while enjoying the bonding complexity reductions of serial mode

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9053066B2NAND flash memory interface

Publication Date: 2015.06.09 SANDISK TECHNOLOGIES LLC

AI summary

A NAND flash memory chip has a configurable interface that can communicate with a NAND flash memory controller using either parallel communication or serial communication. Serial communication requires fewer channels. Control information from the NAND flash memory controller uses a small number of channels. Double Data Rate (DDR) communication provides serial communication with adequate data transfer speed.