NAND Flash Control Lines Using Loop-Dependent Charging Current
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Solution Overview
Problem
Current approaches to reduce peak current consumption in NAND flash memory devices often lead to increased programming time and performance degradation, as they either fail to effectively manage peak current spikes or introduce additional steps that slow down the programming process.
Innovation Solution
The implementation of a loop-dependent adjustment of the threshold detection parameter VHSATGT, which allows for regulated to unregulated charging transitions based on predicted parasitic capacitance, optimizing peak current reduction while minimizing the impact on programming time, by analyzing data patterns on control lines to adjust charging currents accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If regulated charging current is used for all control lines throughout the programming cycle, then peak current consumption is reduced, but programming time increases significantly
Solution Approach 1:
The patent applies dynamic charging current regulation by transitioning from regulated to unregulated charging current based on the programming loop phase. During early loops when parasitic capacitance is high, regulated current is used to limit peak current. In later loops when capacitance is discharged, unregulated current is applied to speed up programming. This dynamic adjustment resolves the contradiction by adapting the charging strategy to the actual circuit state rather than using a fixed approach throughout the entire programming cycle.
Solution Approach 2:
The patent implements preliminary action by pre-charging control lines to inhibit voltage levels before the main programming operation begins. This pre-charging phase prepares the control lines in advance, reducing the capacitive loading effect during subsequent programming loops. By performing this preparatory action beforehand, the system can use more aggressive charging currents during the main programming phase without experiencing excessive peak current spikes, thus resolving the time-current tradeoff.
2Productivity
If unregulated charging current is used to speed up programming, then programming time is reduced, but peak current spikes increase causing malfunctions
Solution Approach 1:
The patent employs periodic action by alternating between regulated and unregulated charging current phases based on the programming loop counter. Early programming loops use regulated current to ensure stability and prevent current spikes. Later loops transition to unregulated current to maximize programming speed. This periodic switching strategy allows the system to maintain reliability during critical phases while achieving high productivity during safe operating windows, effectively resolving the contradiction between speed and stability.
Solution Approach 2:
The patent implements feedback control by monitoring the programming loop phase and adjusting the charging current regulation accordingly. The control circuitry uses loop-dependent logic to determine when to switch between regulated and unregulated modes. This feedback mechanism ensures that unregulated current is only applied when it will not cause malfunctions, while still achieving fast programming speeds when conditions permit, thus resolving the reliability-productivity contradiction.
3Loss of energy
If regulated charging current is applied during all phases, then peak current is controlled, but operational performance degrades due to increased programming time
Solution Approach 1:
The patent applies segmentation by dividing the programming cycle into distinct phases: an initial phase using regulated charging current for peak current control, and a subsequent phase using unregulated charging current for high-speed programming. By segmenting the programming process into these functionally different stages, the system can optimize for current control when necessary and for speed when safe, thereby resolving the contradiction between peak current management and operational performance.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the charging current regulation parameter based on the programming loop phase. The system transitions from a regulated current parameter (limiting peak current) to an unregulated current parameter (maximizing charging speed) as the programming progresses. This parameter adaptation allows the system to maintain good peak current control during critical early phases while achieving high operational performance during later phases, effectively resolving the contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces peak current spikes and optimizes programming time, ensuring efficient peak current management without degrading operational performance, thereby enhancing the operational efficiency of NAND flash memory devices.
Implementation Method 1
based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines
Data Source
AI summary
An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.